Bug: ports mentioned in verilog file are taken as declaration.

[rahultanwar10]

There are two types of coding style in module's ports declaration.

FIRST:
module module_name (
input in1,
input in2,
output out1);

In ast output this is what i get:
Description
ModuleDef (name: module_name)
Paramlist
Portlist
Ioport
Input (name: in1)
Ioport
Input (name: in2)
Ioport
Output (name: out1)

SECOND:
module module_name (in1, in2, out1);
input in1;
input in2;
output out1;

In ast output this is what i get:
Description
ModuleDef (name: module_name)
Paramlist
Portlist
Port (name: in1)
Port (name: in2)
Port (name: out1)
Decl
Input (name: in1)
Decl
Input (name: in2)
Decl
Output (name: out1)

Now, I am working on some project in which i need to extract the port name and its direction. I have used the portlist class to find its direction (input or output or inout). So FIRST method works fine for me. But in SECOND case, i get the port names but not the direction. Direction is mentioned in the Decl class not in the Portlist class. So, my code is breaking. I have done a workaround in my project but i strongly feel that information about ports should be in Portlist class instead of Decl class. That's why i am opening this issue. If there is something that i am understanding wrong then please let me know.