README.md

Docker Container with FPGA tools

About tools:

• Iverilog - Tool for compiling ALL of the Verilog HDL, as described in the IEEE-1364 standard.
• Yosys - Open SYnthesis Suite.
• Verilator - Open-source SystemVerilog simulator and lint system.
• Verible - Suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server.
• Cocotb - Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
• PyUVM - The UVM written in Python.
• MyHDL - Package for using Python as a hardware description and verification language.
• OpenLane - Automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
• UVM-Python - Python and cocotb-based port of the SystemVerilog Universal Verification Methodology (UVM) 1.2.
• VUnit - Unit testing framework for VHDL/SystemVerilog.

Clone repository:

git clone https://github.com/RDSik/FPGA-Tools-Docker.git
cd FPGA-Tools-Docker

Or pull image:

docker pull r0d0s/fpga_tools:latest

Build image:

docker build -t r0d0s/fpga_tools:latest .

Run container:

docker run -it r0d0s/fpga_tools:latest