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board_checklist.csv
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"Board name and version #:" "Proto Review" "Group Review"
"Reviewed by:"
Schematic
Frame:
"Does the frame have the proper CC attribution? (Frame- Letter/Ledger, CC 4.0)" "MH"
"Is the frame large enough to fit all the parts within it?" "MH"
General:
"Is there a SparkFun Logo?" "MH"
"Is there an OSHW logo?" "MH"
"Is proper attribution given to the original designer?" "MH"
"Is “Revised by:” included?" "NA"
"Is the reviser name included?" "NA"
"Do all nets use flag indicators?" "MH"
"Are all net lines 0.006”?" "MH"
"Are there any 4-way junctions?" "MH"
"Are junction dots used for all 3-wire connections?" "MH"
"Are the fiducials in the lower right corner?" "MH"
"Are the standoffs in the lower right corner?" "MH"
"Are dashed grey lines (symbol layer) used to clearly separate different areas?" "MH"
"Is the version number correct?" "MH"
"Is this included on all sheets?" "MH"
"Do all GND connections use the GND symbol?" "MH"
"Are all GND symbols oriented correctly?" "MH"
"Do all VCC connections use the VCC symbol?" "MH"
"Are all VCC connections oriented correctly?" "MH"
"Is the VCC range clearly labeled?" "MH"
"Do any part names have “$” in them?" "MH"
"Do any part names have “/.~” in them? (Multiple sheets)" "MH"
"Are any jumpers labeled clearly by their function and possible settings?" "MH"
"Are any appropriate warnings (voltage conversion, sensitive I/O) labeled?" "MH"
"Is the I2C address in the schematic?" "NA"
"Are any notes of two versions of the board in the schematic (3.3V regulator vs 5V regulator)?" "NA"
"Are all components named correctly (proper prefix)?" "MH"
* "Does every component have a PROD_ID?" "MH"
* "Does every component have a VALUE?" "MH"
"Do all symbols have >Name on Names layer?" "MH"
"Do all symbols have >Value on Values layer?" "MH"
"PCB "
Mechanical:
"Is board frame 0.008”?" "MH"
"Are 0.1” headers lined up on 0.1” grid?" "MH"
"Are opposing 0.1” headers spaced to fit into a breadboard?" "MH"
"Are all test points on a 0.1” grid?" "MH"
"Does the board have standoffs?" "MH"
"Can standoffs/screws be used clear of other parts?" "MH"
"IS the FTDI connector accessible (can you slide an FTDI board onto the connector)?" "NA"
"Is the FTDI connector oriented so the FTDI breakout can be slid on properly (IC side up, header side down)?" "NA"
"With all layers on, are vias tented correctly?" "MH"
"Are corners rounded correctly?" "MH"
"Are all components that hang over the board edge on the same side of the board?" "MH"
"Are dimension lines properly spaced for V-scoring (lines on a 0.020” center-to-center spacing)?" "MH"
"Does this board adhere to the standard manufacturing process? (Kitting time, glue curing, humidor time, etc.)" "MH"
Layout:
"Are 0603 components the 'correct' component footprint?" "MH"
"Are traces 0.01”?" "MH"
* "If they must be smaller, are they at least 0.006”?" "MH"
* "Is there at least 0.006” between traces?" "MH"
"Are vias 0.02”?" "MH"
* "If they must be smaller, are they at least 0.01”?" "MH"
"If it's for soldering,is it actually a 1-pin header so it's reflected on the schematic?" "MH"
"Does the board use I2C?" "MH"
"Is it the standard I2C footprint?"
"Pull-up resistor isolation jumper present?"
"Are all PTH components selective solder compatible?" "MH"
"Are all PTH components for selective soldering populated on the same side?" "MH"
"Are traces to SMT components limited to 1 pin per incoming trace?" "MH"
"Are there no natural bridges on SMT components?" "MH"
"Do SMT components with 6 or more leads have a limited ground pour underneath the IC?" "MH"
"Do any BGA components have 16 or less leads? " "NA"
"Do all leads have test points?" "MH"
"Are any components or ground pour within 0.05” of the board edge?" "MH"
"Is the direction of TX/RX serial connections correct?" "NA"
"Are the TX/RX pins of the FTDI properly connected?" "NA"
"Are all traces straight lines (only 45 degree angles)?" "MH"
"Are there only T-intersections of traces?" "MH"
"Are traces routed AWAY from centers of pads/pins? " "MH"
"Are traces routed away from the component, with symmetrical routing?" "MH"
"Do all footprints pass 1:1 check?"
"Are bottom side center NC pads pasted?" "NA"
"Are bottom side center ground pads 50% pasted?" "MH"
"Are all QFN components with 6 or more leads 75% pasted?" "MH"
"Are center pad cream apertures properly reduced?" "MH"
"Is there any solder mask between pads on fine pitch components?" "MH"
"On white solder mask pcbs, is there any solder mask between leads on large SMT components?" "NA"
"Are all utilized pins contactable by test point (preferably through-hole)?" "MH"
"If test point cannot be through-hole, is the test-point device from the SFE-Library used?"
"If vias must be used as test points, are they 20 mil and unmasked?"
"Is the copper pour set to 0.012” isolate?" "MH"
"Are any traces exposed? " "MH"
"Is there a version number in the copper?" "MH"
"Is the version number incremented properly?"
"Are there 2 fiducials in opposite corners?" "MH"
* "Does it pass SparkFun DRC?" "MH"
* "Does it pass DRC check with “Check angle” on?" "MH"
* "Does it pass DRC with top/bottom keepout layers on?" "MH"
"Are there airwires after ratsnest?" "MH"
"Does this design use any “KIT” devices?" "NA"
"If so, are all of the parts on the correct side with correct masking (i.e. the TSTOP and BSTOP expose the correct side of the annular ring for soldering)"
Documentation:
"Do all footprints have >Name on tNames layer?" "MH"
"Do all footprints have >Value on tValues layer?" "MH"
"Is there a note for a 4-layer board?" "MH"
"Are the board dimensions included(on a new layer)?" "MH"
"Are the board dimensions on 0.05” /0.01” grid?" "MH"
* "Are routed-out areas labeled “ROUTE OUT”?" "NA"
"Is the CC/Design By included in tDocu?" "MH"
"Is the designer name included in tDocu?" "MH"
"Is “Revised by:” included in tDocu?" "NA"
"Is the reviser name included in tDocu?"
Silkscreen/Labeling:
"Is the name of the board on the board?"
"Do all footprints have 0.008” silk footprint?" "MH"
"Are all LEDs labeled with their purpose?" "MH"
"Are all connectors labeled with their purpose?" "MH"
"Are battery terminals labeled +/- correctly?" "MH"
"Are all jumpers labeled?" "MH"
"If it is a 3-way jumper, is there a label on each side of the jumper?" "NA"
"Are axes labeled correctly?" "NA"
"Are there warning labels for high voltage areas?" "NA"
"Are all switches labeled?" "MH"
"Are all buttons labeled?" "MH"
"Are active low pins labeled clearly?" "MH"
"Are all PTH pins labeled?" "MH"
"Are there pin labels on both sides of the board?" "NA"
"Are they correct on both sides of the board?"
"Are all labels lined up properly?" "MH"
"Is all text at least 0.032”?" "MH"
"Is all text 15% ratio?" "MH"
"Is all text vector font?" "MH"
"Does the FTDI connector have BLK/GRN labeled correctly?" "NA"
"Does the ICSP have pin 1 labeled?" "MH"
"Do all components have polarity or pin 1 labeled?" "MH"
"Are there check labels for different versions of the board (3.3V vs 5V)?" "NA"
"Is the SparkFun Logo on the board?" "MH"
"Is the OSHW logo on the board?" "MH"
"Is any silkscreen overlaid on vias?" "MH"
"Is there a URL for any kits or unique boards?"
"Things to discuss"
"Uniform part direction with parts of the same footprint or type " "Orientation thru the oven will be a thing. Info on tooling strips."
"Uniform polarity direction for all polarized components" "It's a dream"
"Unused pins adjacent to used pins, including power and gnd pins, must also have test points " "place test point on via to expose copper"
"Component temperature ranges/Moisture sensitivity levels for new components considered " "List of standard temps, humidity levels, addition to Sparkle part for MSL/ reflow temps, MSL below 2, minimum reflow temp (pre-design checklist)"
"Engineers add data sheets to Sparkle for any new parts found" "Add comments to datasheets for NDA things"
"Minimize number of unique components "
"Natural bridges vs. polygons for motor driver ICs" "Ok with no natural bridges or polygons on pins, add trestrict between all adjacent pads (ADD to part creation list)"
"Double-sided acceptable only with all SMT, no mix " "discuss more"
"List of selective-solder non-compatible parts" "add to QC repo"
"Test strategy must be established during prototyping stage " "scheduled DFT meeting?"
"What layer to label for routing out, board dimensions" route
"Standard for LED color selection (red for power, blue for STAT, green for TX, yellow for RX)" YES.
"Label for polarity outside of package for visibility after production" YES.
"Reference designators for each part on silkscreen on the boards" "more diligent on board files for name values, silk labels only on important hackable parts for user "
"Part Selection List"
"No EOL components "
"No sole-source components if possible "
"Multiple manufacturers specified with minimal part cost difference "
"Adhere to stock parts list - minimize deviations (part of scrubbing process w/ outside collaborators)"