From 7985c6c5bf6b38ddcc126c2a1aeba17d754eeea0 Mon Sep 17 00:00:00 2001 From: Winor Chen Date: Tue, 11 Dec 2018 23:13:11 -0600 Subject: [PATCH] Update testbench, aid in testing --- testing/canonical-phase3/project-phase3-testbench.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/testing/canonical-phase3/project-phase3-testbench.v b/testing/canonical-phase3/project-phase3-testbench.v index 702df02..9cb4f67 100644 --- a/testing/canonical-phase3/project-phase3-testbench.v +++ b/testing/canonical-phase3/project-phase3-testbench.v @@ -202,13 +202,13 @@ module cpu_ptb(); assign ICacheReq = DUT.pcRegister.we; // Signal indicating a valid instruction read request to cache - assign ICacheHit = ~DUT.i_miss; + assign ICacheHit = ~DUT.i_miss & DUT.pcRegister.we; // Signal indicating a valid instruction cache hit - assign DCacheReq = DUT.mem_inst[15:12]==4'b1000; + assign DCacheReq = DUT.mem_inst[15:13]==4'b100; // Signal indicating a valid instruction data read or write request to cache - assign DCacheHit = ~DUT.d_miss; + assign DCacheHit = ~DUT.d_miss & (DUT.mem_inst[15:13]==4'b100); // Signal indicating a valid data cache hit