From 399fffb67c23d38d2f74876d1efa6b01a5c82bd2 Mon Sep 17 00:00:00 2001 From: Winor Chen Date: Tue, 11 Dec 2018 04:17:12 -0600 Subject: [PATCH 1/7] Fix some port warnings on cache fill FSM --- p3/memory/Cache_fill_FSM.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/p3/memory/Cache_fill_FSM.v b/p3/memory/Cache_fill_FSM.v index 09355f0..7937bcd 100644 --- a/p3/memory/Cache_fill_FSM.v +++ b/p3/memory/Cache_fill_FSM.v @@ -31,16 +31,16 @@ wire [15:0] current_address_plus_two, current_address_plus_two_c; Register_4bit COUNT_REG(clk, ~miss_detected | ~rst_n | (count_reg_Q == 8) | arb_force_reset, count_reg_D , (count_reg_Q != 8) & (memory_data_valid), 1'b1, 1'b0, count_reg_Q, ); // holds the current "count state" Register_4bit ADDR_COUNT_REG(clk, ~miss_detected | ~rst_n | arb_force_reset, addr_creg_D, (addr_creg_Q != 9), 1'b1, 1'b0, addr_creg_Q, ); // hold the count of how many address increments were made -Register WORKING_ADDRESS(clk, ~miss_detected | ~rst_n, next_address, 1'b1, 1'b1, 1'b0, current_address); -Register WORKING_ADDRESS_FOR_CACHE(clk, ~miss_detected | ~rst_n, next_address_c, 1'b1, 1'b1, 1'b0, current_address_c); +Register WORKING_ADDRESS(clk, ~miss_detected | ~rst_n, next_address, 1'b1, 1'b1, 1'b0, current_address, ); +Register WORKING_ADDRESS_FOR_CACHE(clk, ~miss_detected | ~rst_n, next_address_c, 1'b1, 1'b1, 1'b0, current_address_c, ); // Incrementer for segment count and delay count adder_4bit_cla_simple COUNT_REQ_INC(,, count_reg_D, count_reg_Q, 1 & miss_detected, 1'b0); adder_4bit_cla_simple COUNT_ADR_INC(,, addr_creg_D, addr_creg_Q, 1 & miss_detected, 1'b0); // Increment the current address by two -adder_16bit_cla_simple ADDRESS_INC(current_address_plus_two, current_address, 2); -adder_16bit_cla_simple ADDRESS_INC_CACHE(current_address_plus_two_c, current_address_c, 2); +adder_16bit_cla_simple ADDRESS_INC(current_address_plus_two, current_address, 16'b0000000000000010); +adder_16bit_cla_simple ADDRESS_INC_CACHE(current_address_plus_two_c, current_address_c, 16'b0000000000000010); // Wire assignments assign base_address = {miss_address[15:4], {4'b0000}}; From fef114fe9fa100662f42edf29259e23963e8e422 Mon Sep 17 00:00:00 2001 From: Winor Chen Date: Tue, 11 Dec 2018 04:47:48 -0600 Subject: [PATCH 2/7] Explicit wire connections for cache fill FSM and IFID register --- p3/memory/Cache_fill_FSM.v | 5 ++--- p3/registers/IFID_Pipe_Register.v | 4 ++-- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/p3/memory/Cache_fill_FSM.v b/p3/memory/Cache_fill_FSM.v index 7937bcd..e91d89f 100644 --- a/p3/memory/Cache_fill_FSM.v +++ b/p3/memory/Cache_fill_FSM.v @@ -19,7 +19,6 @@ output EOB; // Register Wires wire [3:0] count_reg_D, count_reg_Q, addr_creg_D, addr_creg_Q; -wire fsm_active; wire [15:0] base_address; // address with 0 offset wire [15:0] current_address; // base address for miss handling. First, fetch from bit offset 0, then 2, 4, 6, 8, 10, 12, 14. wire [15:0] next_address; // next address state @@ -35,8 +34,8 @@ Register WORKING_ADDRESS(clk, ~miss_detected | ~rst_n, next_address, 1'b1, 1'b1, Register WORKING_ADDRESS_FOR_CACHE(clk, ~miss_detected | ~rst_n, next_address_c, 1'b1, 1'b1, 1'b0, current_address_c, ); // Incrementer for segment count and delay count -adder_4bit_cla_simple COUNT_REQ_INC(,, count_reg_D, count_reg_Q, 1 & miss_detected, 1'b0); -adder_4bit_cla_simple COUNT_ADR_INC(,, addr_creg_D, addr_creg_Q, 1 & miss_detected, 1'b0); +adder_4bit_cla_simple COUNT_REQ_INC(,, count_reg_D, count_reg_Q, {3'b000 , miss_detected}, 1'b0); +adder_4bit_cla_simple COUNT_ADR_INC(,, addr_creg_D, addr_creg_Q, {3'b000 , miss_detected}, 1'b0); // Increment the current address by two adder_16bit_cla_simple ADDRESS_INC(current_address_plus_two, current_address, 16'b0000000000000010); diff --git a/p3/registers/IFID_Pipe_Register.v b/p3/registers/IFID_Pipe_Register.v index 7e592ab..8f6e30b 100644 --- a/p3/registers/IFID_Pipe_Register.v +++ b/p3/registers/IFID_Pipe_Register.v @@ -6,6 +6,6 @@ */ module IFID_Pipe_Register(input clk, input rst, input WE, input flush, input [15:0] inst_next, output[15:0] inst, input[15:0] pc_in, output[15:0] pc_out); // xor $0, $0, $0 is the bubble instruction - Register IFID(.clk(clk), .rst(rst), .D(flush?16'h2000:inst_next), .WriteReg(WE), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(inst)); - Register IFID2(.clk(clk), .rst(rst), .D(flush?16'h0000:pc_in), .WriteReg(WE), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(pc_out)); + Register IFID(.clk(clk), .rst(rst), .D(flush?16'h2000:inst_next), .WriteReg(WE), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(inst), .Bitline2()); + Register IFID2(.clk(clk), .rst(rst), .D(flush?16'h0000:pc_in), .WriteReg(WE), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(pc_out), .Bitline2()); endmodule From 51e9cb02255a5053fc6aea8eb6001e05fa77ae87 Mon Sep 17 00:00:00 2001 From: Winor Chen Date: Tue, 11 Dec 2018 04:51:24 -0600 Subject: [PATCH 3/7] Fix more warnings --- p3/registers/PipelineRegister.v | 34 ++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/p3/registers/PipelineRegister.v b/p3/registers/PipelineRegister.v index 7cc481b..8405e74 100644 --- a/p3/registers/PipelineRegister.v +++ b/p3/registers/PipelineRegister.v @@ -31,21 +31,21 @@ module PipelineRegister( input [3:0] gppr3_in, gppr4_in; output[3:0] gppr3_ou, gppr4_ou; - BitCell hlt(.clk(clk), .rst(rst|flush), .D(hlt_in), .WriteEnable(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(hlt_ou)); - BitCell rfwe(.clk(clk), .rst(rst|flush), .D(RFwe_in), .WriteEnable(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(RFwe_ou)); - BitCell DataWE(.clk(clk), .rst(rst|flush), .D(DataWE_in), .WriteEnable(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(DataWE_ou)); - BitCell ALU1Src(.clk(clk), .rst(rst|flush), .D(ALU1Src_in), .WriteEnable(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(ALU1Src_ou)); - BitCell ALU2Src(.clk(clk), .rst(rst|flush), .D(ALU2Src_in), .WriteEnable(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(ALU2Src_ou)); - - Register_3bit flag(.clk(clk), .rst(rst|flush), .D(flag_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(flag_ou)); - Register_3bit flagwe(.clk(clk), .rst(rst|flush), .D(flagwe_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(flagwe_ou)); - - Register_4bit RFdst(.clk(clk), .rst(rst|flush), .D(RFdst_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(RFdst_ou)); - Register_4bit gppr3(.clk(clk), .rst(rst|flush), .D(gppr3_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(gppr3_ou)); - Register_4bit gppr4(.clk(clk), .rst(rst|flush), .D(gppr4_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(gppr4_ou)); - - Register inst(.clk(clk), .rst(rst), .D(flush?16'h2000 :inst_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(inst_ou)); - Register pc(.clk(clk), .rst(rst|flush), .D(pc_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(pc_ou)); - Register gppr1(.clk(clk), .rst(rst|flush), .D(gppr1_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(gppr1_ou)); - Register gppr2(.clk(clk), .rst(rst|flush), .D(gppr2_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(gppr2_ou)); + BitCell hlt(.clk(clk), .rst(rst|flush), .D(hlt_in), .WriteEnable(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(hlt_ou), .Bitline2()); + BitCell rfwe(.clk(clk), .rst(rst|flush), .D(RFwe_in), .WriteEnable(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(RFwe_ou), .Bitline2()); + BitCell DataWE(.clk(clk), .rst(rst|flush), .D(DataWE_in), .WriteEnable(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(DataWE_ou), .Bitline2()); + BitCell ALU1Src(.clk(clk), .rst(rst|flush), .D(ALU1Src_in), .WriteEnable(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(ALU1Src_ou), .Bitline2()); + BitCell ALU2Src(.clk(clk), .rst(rst|flush), .D(ALU2Src_in), .WriteEnable(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(ALU2Src_ou), .Bitline2()); + + Register_3bit flag(.clk(clk), .rst(rst|flush), .D(flag_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(flag_ou), .Bitline2()); + Register_3bit flagwe(.clk(clk), .rst(rst|flush), .D(flagwe_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(flagwe_ou), .Bitline2()); + + Register_4bit RFdst(.clk(clk), .rst(rst|flush), .D(RFdst_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(RFdst_ou), .Bitline2()); + Register_4bit gppr3(.clk(clk), .rst(rst|flush), .D(gppr3_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(gppr3_ou), .Bitline2()); + Register_4bit gppr4(.clk(clk), .rst(rst|flush), .D(gppr4_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(gppr4_ou), .Bitline2()); + + Register inst(.clk(clk), .rst(rst), .D(flush?16'h2000 :inst_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(inst_ou), .Bitline2()); + Register pc(.clk(clk), .rst(rst|flush), .D(pc_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(pc_ou), .Bitline2()); + Register gppr1(.clk(clk), .rst(rst|flush), .D(gppr1_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(gppr1_ou), .Bitline2()); + Register gppr2(.clk(clk), .rst(rst|flush), .D(gppr2_in), .WriteReg(we), .ReadEnable1(1'b1), .ReadEnable2(1'b0), .Bitline1(gppr2_ou), .Bitline2()); endmodule \ No newline at end of file From 7abc3a2508b2dc54068a5b6aa1adcc71d2596c23 Mon Sep 17 00:00:00 2001 From: Winor Chen Date: Tue, 11 Dec 2018 05:04:51 -0600 Subject: [PATCH 4/7] Further warning fixes, test still passes --- p3/cpu.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/p3/cpu.v b/p3/cpu.v index aa0ffb4..93acca7 100644 --- a/p3/cpu.v +++ b/p3/cpu.v @@ -186,6 +186,8 @@ module cpu(clk, rst_n, hlt, pc); .RFdst_in(mem_RFdst), .RFdst_ou(wb_RFdst), .gppr1_in(mem_DataToBeWrittenToPR), .gppr1_ou(wb_RFwriteData), .flag_in(mem_flag), .flag_ou(wb_flag), - .flagwe_in(mem_flagwe), .flagwe_ou(wb_flagwe) + .flagwe_in(mem_flagwe), .flagwe_ou(wb_flagwe), .DataWE_in(1'b0), + .ALU1Src_in(1'b0), .ALU2Src_in(1'b0), .inst_in({16{1'b0}}), .pc_in({16{1'b0}}), .gppr2_in({16{1'b0}}), .gppr3_in({4{1'b0}}), .gppr4_in({4{1'b0}}), + .ALU1Src_ou(), .ALU2Src_ou(), .inst_ou(), .pc_ou(), .gppr2_ou(), .gppr3_ou(), .gppr4_ou(), .DataWE_ou() ); endmodule \ No newline at end of file From f2ee823a6b1fe8ce506ac3a2ddfa175906bda37b Mon Sep 17 00:00:00 2001 From: Winor Chen Date: Tue, 11 Dec 2018 05:12:05 -0600 Subject: [PATCH 5/7] Further tie down wires which are not used --- p3/cpu.v | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/p3/cpu.v b/p3/cpu.v index 93acca7..d05ef82 100644 --- a/p3/cpu.v +++ b/p3/cpu.v @@ -167,7 +167,9 @@ module cpu(clk, rst_n, hlt, pc); .inst_in(ex_inst), .inst_ou(mem_inst), .gppr1_in(ex_resultToPR), .gppr1_ou(mem_AluResult), .gppr2_in(mem_RFout2_in), .gppr2_ou(mem_DataWriteDataFromPR), - .gppr3_in(ex_RFsrc2), .gppr3_ou(mem_DataWriteSrcReg) + .gppr3_in(ex_RFsrc2), .gppr3_ou(mem_DataWriteSrcReg), + .ALU1Src_ou(), .ALU2Src_ou(), .pc_ou(), .gppr4_ou(), + .ALU1Src_in(1'b0), .ALU2Src_in(1'b0), .pc_in({16{1'b0}}), .gppr4_in(4'b000) ); @@ -190,4 +192,4 @@ module cpu(clk, rst_n, hlt, pc); .ALU1Src_in(1'b0), .ALU2Src_in(1'b0), .inst_in({16{1'b0}}), .pc_in({16{1'b0}}), .gppr2_in({16{1'b0}}), .gppr3_in({4{1'b0}}), .gppr4_in({4{1'b0}}), .ALU1Src_ou(), .ALU2Src_ou(), .inst_ou(), .pc_ou(), .gppr2_ou(), .gppr3_ou(), .gppr4_ou(), .DataWE_ou() ); -endmodule \ No newline at end of file +endmodule From 0f503c4bdb64b4ab1e83ecea5ec93a15024aed2b Mon Sep 17 00:00:00 2001 From: Winor Chen Date: Tue, 11 Dec 2018 05:16:01 -0600 Subject: [PATCH 6/7] Completely eradicated relevant warnings. --- p3/cpu.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/p3/cpu.v b/p3/cpu.v index d05ef82..8db2ba5 100644 --- a/p3/cpu.v +++ b/p3/cpu.v @@ -98,7 +98,7 @@ module cpu(clk, rst_n, hlt, pc); assign id_RFdst = id_inst[11:8]; ControlUnit ctrl(.opcode(id_inst[15:12]), .HLT(id_hlt), .PCwe(pc_we), .RFwe(id_RFwe), .MemWE(id_DataWe), .FLAGwe(id_flagwe), - .ALU2Src(id_ALU2Src), .A2Src(id_A2Src)); + .ALU2Src(id_ALU2Src), .A2Src(id_A2Src), .NeedBranch(), .DwMUX()); assign id_ALU1Src = id_inst[15:13] == 3'b101; @@ -116,7 +116,7 @@ module cpu(clk, rst_n, hlt, pc); .gppr1_in(id_RFout1), .gppr1_ou(ex_RFout1), .gppr2_in(id_RFout2), .gppr2_ou(ex_RFout2), .gppr3_in(id_RFsrc1), .gppr3_ou(ex_RFsrc1), - .gppr4_in(id_RFsrc2), .gppr4_ou(ex_RFsrc2) + .gppr4_in(id_RFsrc2), .gppr4_ou(ex_RFsrc2), .flag_in(3'b000), .flag_ou() ); // EX stage From e7e3c80ffb965e7abe687ecdb39ec731b5c17897 Mon Sep 17 00:00:00 2001 From: Winor Chen Date: Tue, 11 Dec 2018 05:43:33 -0600 Subject: [PATCH 7/7] Tied up HiZ outputs further, passing tests --- p3/memory/Cache_Toplevel.v | 7 +++++-- p3/memory/Memory_Controller.v | 2 ++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/p3/memory/Cache_Toplevel.v b/p3/memory/Cache_Toplevel.v index 4702700..a1fc09e 100644 --- a/p3/memory/Cache_Toplevel.v +++ b/p3/memory/Cache_Toplevel.v @@ -96,14 +96,17 @@ module Cache_Toplevel(clk, rst, Address_Oper, r_enabled, cacheop, Data_In, Data_ assign hit_way_1 = valids[1] & (tag_in == tag_out_1); assign miss_occurred = r_enabled & ~(hit_way_0 | hit_way_1); assign hit_occurred = r_enabled & (hit_way_0 | hit_way_1); - assign Data_Out = DataArray_Out; + assign Data_Out = r_enabled ? + block_decode_data != {128{1'b0}} ? + DataArray_Out + : {16{1'b0}} + : {16{1'b0}}; assign tag_in = Address_Oper[15:10]; assign tag_out_0 = tag_raw_out_0[5:0]; assign tag_out_1 = tag_raw_out_1[5:0]; assign set_index = Address_Oper[9:4]; assign valids = {tag_raw_out_1[7], tag_raw_out_0[7]}; assign block_decode_ze = {{64{1'b0}}, block_decode}; - //assign block_decode_data = == 0 ? block_decode_ze : block_decode_ze << 64; assign word_select = Address_Oper[3:1]; // For FSM designer: change these address bits to change word offset index when filling assign lrus_n = {tag_raw_out_1[6], tag_raw_out_0[6]}; diff --git a/p3/memory/Memory_Controller.v b/p3/memory/Memory_Controller.v index 67a2de0..c21b6af 100644 --- a/p3/memory/Memory_Controller.v +++ b/p3/memory/Memory_Controller.v @@ -72,6 +72,8 @@ module Memory_Controller(clk, rst, if_we, dm_we, d_enable, if_addr, dm_addr, // THE Main Memory Module memory4c MAIN_MEMORY(.data_out(mm_out), .data_in(mm_in), .addr(work_and_store_address), .enable((|miss_states & ~mm_ren) | update_enable | store_data_hit_enable), .wr(update_enable | store_data_hit_enable), .clk(clk), .rst(rst), .data_valid(valid_data_state)); + assign dm_data_out = cacheop_1 == 2'b01 ? {16{1'b0}} : {16{1'bz}}; + assign store_data_hit_enable = store & ~fsm_active; assign update_enable = miss_states == 2'b01 & store & fsm_tag_fill;