From b795c3801b402bfb5e63990a026d8209117a11eb Mon Sep 17 00:00:00 2001 From: Winor Chen Date: Tue, 11 Dec 2018 23:24:01 -0600 Subject: [PATCH] Tweak testbench a bit --- testing/canonical-phase3/project-phase3-testbench.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testing/canonical-phase3/project-phase3-testbench.v b/testing/canonical-phase3/project-phase3-testbench.v index 9cb4f67..bad8352 100644 --- a/testing/canonical-phase3/project-phase3-testbench.v +++ b/testing/canonical-phase3/project-phase3-testbench.v @@ -199,10 +199,10 @@ module cpu_ptb(); assign MemDataOut = DUT.mem_DataReadData; // If there's a memory read in this cycle, this is the data being read out of memory (16 bits) - assign ICacheReq = DUT.pcRegister.we; + assign ICacheReq = ~DUT.hlt; // Signal indicating a valid instruction read request to cache - assign ICacheHit = ~DUT.i_miss & DUT.pcRegister.we; + assign ICacheHit = ~DUT.i_miss & ~DUT.hlt; // Signal indicating a valid instruction cache hit assign DCacheReq = DUT.mem_inst[15:13]==4'b100;