Skip to content

Commit 3cb550c

Browse files
0xAX0xAX
committed
Add KernelStructures/idt.md
1 parent 6dca6b1 commit 3cb550c

File tree

3 files changed

+199
-0
lines changed

3 files changed

+199
-0
lines changed

‎KernelStructures/README.md

+7
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
# Internal `system` structures of the Linux kernel
2+
3+
This is not usual chapter of `linux-insides`. As you may understand from the title, it mostly describes
4+
internal `system` structures of the Linux kernel. Like `Interrupt Descriptor Table`, `Global Descriptor
5+
Table` and many many more.
6+
7+
Most of information is taken from official [Intel](http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html) and [AMD](http://developer.amd.com/resources/developer-guides-manuals/) manuals.

‎KernelStructures/idt.md

+190
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,190 @@
1+
interrupt-descriptor table (IDT)
2+
================================================================================
3+
4+
Three general interrupt & exceptions sources:
5+
6+
* Exceptions - sync;
7+
* Software interrupts - sync;
8+
* External interrupts - async.
9+
10+
Types of Exceptions:
11+
12+
* Faults - are precise exceptions reported on the boundary `before` the instruction causing the exception. The saved `%rip` points to the faulting instruction;
13+
* Traps - are precise exceptions reported on the boundary `following` the instruction causing the exception. The same with `%rip`;
14+
* Aborts - are imprecise exceptions. Because they are imprecise, aborts typically do not allow reliable program restart.
15+
16+
`Maskable` interrupts trigger the interrupt-handling mechanism only when RFLAGS.IF=1. Otherwise they are held pending for as long as the RFLAGS.IF bit is cleared to 0.
17+
18+
`Nonmaskable` interrupts (NMI) are unaffected by the value of the rFLAGS.IF bit. However, the occurrence of an NMI masks further NMIs until an IRET instruction is executed.
19+
20+
Specific exception and interrupt sources are assigned a fixed vector-identification number (also called an “interrupt vector” or simply “vector”). The interrupt vector is used by the interrupt-handling mechanism to locate the system-software service routine assigned to the exception or interrupt. Up to
21+
256 unique interrupt vectors are available. The first 32 vectors are reserved for predefined exception and interrupt conditions. They are defined in the [arch/x86/include/asm/traps.h](http://lxr.free-electrons.com/source/arch/x86/include/asm/traps.h#L121) header file:
22+
23+
```
24+
/* Interrupts/Exceptions */
25+
enum {
26+
X86_TRAP_DE = 0, /* 0, Divide-by-zero */
27+
X86_TRAP_DB, /* 1, Debug */
28+
X86_TRAP_NMI, /* 2, Non-maskable Interrupt */
29+
X86_TRAP_BP, /* 3, Breakpoint */
30+
X86_TRAP_OF, /* 4, Overflow */
31+
X86_TRAP_BR, /* 5, Bound Range Exceeded */
32+
X86_TRAP_UD, /* 6, Invalid Opcode */
33+
X86_TRAP_NM, /* 7, Device Not Available */
34+
X86_TRAP_DF, /* 8, Double Fault */
35+
X86_TRAP_OLD_MF, /* 9, Coprocessor Segment Overrun */
36+
X86_TRAP_TS, /* 10, Invalid TSS */
37+
X86_TRAP_NP, /* 11, Segment Not Present */
38+
X86_TRAP_SS, /* 12, Stack Segment Fault */
39+
X86_TRAP_GP, /* 13, General Protection Fault */
40+
X86_TRAP_PF, /* 14, Page Fault */
41+
X86_TRAP_SPURIOUS, /* 15, Spurious Interrupt */
42+
X86_TRAP_MF, /* 16, x87 Floating-Point Exception */
43+
X86_TRAP_AC, /* 17, Alignment Check */
44+
X86_TRAP_MC, /* 18, Machine Check */
45+
X86_TRAP_XF, /* 19, SIMD Floating-Point Exception */
46+
X86_TRAP_IRET = 32, /* 32, IRET Exception */
47+
};
48+
```
49+
50+
Error Codes
51+
--------------------------------------------------------------------------------
52+
53+
The processor exception-handling mechanism reports error and status information for some exceptions using an error code. The error code is pushed onto the stack by the exception-mechanism during the control transfer into the exception handler. The error code has two formats:
54+
55+
* most error-reporting exceptions format;
56+
* page fault format.
57+
58+
Here is format of selector error code:
59+
60+
```
61+
31 16 15 3 2 1 0
62+
+-------------------------------------------------------------------------------+
63+
| | | T | I | E |
64+
| Reserved | Selector Index | - | D | X |
65+
| | | I | T | T |
66+
+-------------------------------------------------------------------------------+
67+
```
68+
69+
Where:
70+
71+
* `EXT` - If this bit is set to 1, the exception source is external to the processor. If cleared to 0, the exception source is internal to the processor;
72+
* `IDT` - If this bit is set to 1, the error-code selector-index field references a gate descriptor located in the `interrupt-descriptor table`. If cleared to 0, the selector-index field references a descriptor in either the `global-descriptor table` or local-descriptor table `LDT`, as indicated by the `TI` bit;
73+
* `TI` - If this bit is set to 1, the error-code selector-index field references a descriptor in the `LDT`. If cleared to 0, the selector-index field references a descriptor in the `GDT`.
74+
* `Selector Index` - The selector-index field specifies the index into either the `GDT`, `LDT`, or `IDT`, as specified by the `IDT` and `TI` bits.
75+
76+
Page-Fault Error Code format is:
77+
78+
```
79+
31 4 3 2 1 0
80+
+-------------------------------------------------------------------------------+
81+
| | | R | U | R | - |
82+
| Reserved | I/D | S | - | - | P |
83+
| | | V | S | W | - |
84+
+-------------------------------------------------------------------------------+
85+
```
86+
87+
Where:
88+
89+
* `I/D` - If this bit is set to 1, it indicates that the access that caused the page fault was an instruction fetch;
90+
* `RSV` - If this bit is set to 1, the page fault is a result of the processor reading a 1 from a reserved field within a page-translation-table entry;
91+
* `U/S` - If this bit is cleared to 0, an access in supervisor mode (`CPL=0, 1, or 2`) caused the page fault. If this bit is set to 1, an access in user mode (CPL=3) caused the page fault;
92+
* `R/W` - If this bit is cleared to 0, the access that caused the page fault is a memory read. If this bit is set to 1, the memory access that caused the page fault was a write;
93+
* `P` - If this bit is cleared to 0, the page fault was caused by a not-present page. If this bit is set to 1, the page fault was caused by a page-protection violation.
94+
95+
Interrupt Control Transfers
96+
--------------------------------------------------------------------------------
97+
98+
The IDT may contain any of three kinds of gate descriptors:
99+
100+
* `Task Gate` - contains the segment selector for a TSS for an exception and/or interrupt handler task;
101+
* `Interrupt Gate` - contains segment selector and offset that the processor uses to transfer program execution to a handler procedure in an interrupt handler code segment;
102+
* `Trap Gate` - contains segment selector and offset that the processor uses to transfer program execution to a handler procedure in an exception handler code segment.
103+
104+
General format of gates is:
105+
106+
```
107+
127 96
108+
+-------------------------------------------------------------------------------+
109+
| |
110+
| Reserved |
111+
| |
112+
+--------------------------------------------------------------------------------
113+
95 64
114+
+-------------------------------------------------------------------------------+
115+
| |
116+
| Offset 63..32 |
117+
| |
118+
+-------------------------------------------------------------------------------+
119+
63 48 47 46 44 42 39 34 32
120+
+-------------------------------------------------------------------------------+
121+
| | | D | | | | | | |
122+
| Offset 31..16 | P | P | 0 |Type |0 0 0 | 0 | 0 | IST |
123+
| | | L | | | | | | |
124+
-------------------------------------------------------------------------------+
125+
31 16 15 0
126+
+-------------------------------------------------------------------------------+
127+
| | |
128+
| Segment Selector | Offset 15..0 |
129+
| | |
130+
+-------------------------------------------------------------------------------+
131+
```
132+
133+
Where
134+
135+
* `Selector` - Segment Selector for destination code segment;
136+
* `Offset` - Offset to handler procedure entry point;
137+
* `DPL` - Descriptor Privilege Level;
138+
* `P` - Segment Present flag;
139+
* `IST` - Interrupt Stack Table;
140+
* `TYPE` - one of: Local descriptor-table (LDT) segment descriptor, Task-state segment (TSS) descriptor, Call-gate descriptor, Interrupt-gate descriptor, Trap-gate descriptor or Task-gate descriptor.
141+
142+
An `IDT` descriptor is represented by the following structure in the Linux kernel (only for `x86_64`):
143+
144+
```C
145+
struct gate_struct64 {
146+
u16 offset_low;
147+
u16 segment;
148+
unsigned ist : 3, zero0 : 5, type : 5, dpl : 2, p : 1;
149+
u16 offset_middle;
150+
u32 offset_high;
151+
u32 zero1;
152+
} __attribute__((packed));
153+
```
154+
155+
which is defined in the [arch/x86/include/asm/desc_defs.h](http://lxr.free-electrons.com/source/arch/x86/include/asm/desc_defs.h#L51) header file.
156+
157+
A task gate descriptor does not contain `IST` field and its format differs from interrupt/trap gates:
158+
159+
```C
160+
struct ldttss_desc64 {
161+
u16 limit0;
162+
u16 base0;
163+
unsigned base1 : 8, type : 5, dpl : 2, p : 1;
164+
unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
165+
u32 base3;
166+
u32 zero1;
167+
} __attribute__((packed));
168+
```
169+
170+
Exceptions During a Task Switch
171+
--------------------------------------------------------------------------------
172+
173+
An exception can occur during a task switch while loading a segment selector. Page faults can also occur when accessing a TSS. In these cases, the hardware task-switch mechanism completes loading the new task state from the TSS, and then triggers the appropriate exception mechanism.
174+
175+
**In long mode, an exception cannot occur during a task switch, because the hardware task-switch mechanism is disabled.**
176+
177+
Nonmaskable interrupt
178+
--------------------------------------------------------------------------------
179+
180+
**TODO**
181+
182+
API
183+
--------------------------------------------------------------------------------
184+
185+
**TODO**
186+
187+
Interrupt Stack Table
188+
--------------------------------------------------------------------------------
189+
190+
**TODO**

‎SUMMARY.md

+2
Original file line numberDiff line numberDiff line change
@@ -77,5 +77,7 @@
7777
* [Linux kernel development](Misc/contribute.md)
7878
* [Write and Submit your first Linux kernel Patch]()
7979
* [Data types in the kernel]()
80+
* [KernelStructures](KernelStructures/README.md)
81+
* [IDT](KernelStructures/idt.md)
8082
* [Useful links](LINKS.md)
8183
* [Contributors](contributors.md)

0 commit comments

Comments
 (0)