Entry points

Edit entry point state after creation

Variables

Give name to locations in RAM

StateChange

Test simplify

Subroutine

Signal processor status at the beginning of each subroutine

Recursive subroutines

Test simplify

Analysis / CPU

`jump_tables` test

missing test cases

ROM

Test ExLoROM

Test ExHiROM

Test SDD-1

Interface

Show loading visually

Misc

Verify there are no memory leaks