al422b_2rgb_8s.sdc

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# THIS IS A WIZARD-GENERATED FILE.                           
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# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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# Clock constraints

create_clock -name "in_clk" -period 20.000ns [get_ports {in_clk}]


# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks

# Automatically calculate clock uncertainty to jitter and other effects.
#derive_clock_uncertainty
# Not supported for family MAX3000A

# tsu/th constraints

set_input_delay -clock "in_clk" -max 5ns [get_ports {in_data*}] 
set_input_delay -clock "in_clk" -min 4.000ns [get_ports {in_data*}] 

set_input_delay -clock "in_clk" -max 5ns [get_ports {in_nrst*}] 
set_input_delay -clock "in_clk" -min 5ns [get_ports {in_nrst*}] 

# tco constraints

# tpd constraints