al422b_2rgb_8s.sdc.bak

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# Clock constraints

create_clock -name "in_clk" -period 20.000ns [get_ports {in_clk}] -waveform {0.000 0.000}


# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks

# Automatically calculate clock uncertainty to jitter and other effects.
#derive_clock_uncertainty
# Not supported for family MAX3000A

# tsu/th constraints

set_input_delay -clock "in_clk" -max 19ns [get_ports {in_data}] 
set_input_delay -clock "in_clk" -min 1.000ns [get_ports {in_data}] 


# tco constraints

# tpd constraints