al422b_2rgb_8s_tb.v.bak

`timescale 1 ps/ 1 ps
module al422b_2rgb_8s_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg in_clk;
reg [7:0] in_data;
reg in_nrst;
// wires                                               
wire al422_nrst;
wire led_clk;
wire led_lat;
wire led_oe;
wire [4:0]  led_row;
wire [2:0]  rgb1;
wire [2:0]  rgb2;

// assign statements (if any)                          
al422b_2rgb_8s i1 (
// port map - connection between master ports and signals/registers   
	.al422_nrst(al422_nrst),
	.in_clk(in_clk),
	.in_data(in_data),
	.in_nrst(in_nrst),
	.led_clk(led_clk),
	.led_lat(led_lat),
	.led_oe(led_oe),
	.led_row(led_row),
	.rgb1(rgb1),
	.rgb2(rgb2)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
                                                       
// --> end                                             
$display("Running testbench");                       
end                                                    
always                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin                          
                                                       
@eachvec;                                              
// --> end                                             
end                                                    
endmodule