interface_v2_1_0.mpd

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## Filename:          D:\MVB\MVB_CPU\pcores/interface_v1_00_a/data/interface_v2_1_0.mpd
## Description:       Microprocessor Peripheral Description
## Date:              Tue Nov 06 11:55:11 2018 (by Create and Import Peripheral Wizard)
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BEGIN interface

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
## Bus Interfaces
BUS_INTERFACE BUS=SFSL, BUS_STD=FSL, BUS_TYPE=SLAVE
BUS_INTERFACE BUS=MFSL, BUS_STD=FSL, BUS_TYPE=MASTER

## Peripheral ports
PORT CLK_3M = CLK_3M, DIR=I, SIGIS=Clk
PORT ENCODE_DATA =ENCODE_DATA, DIR=O, VEC=[0:31]
PORT DECODE_DATA =DECODE_DATA, DIR=I, VEC=[0:31]
PORT ENCODE_READ_EN=ENCODE_READ_EN, DIR=I
PORT DECODE_WRITE_EN=DECODE_WRITE_EN, DIR=I
PORT DECODE_CLK_3M=DECODE_CLK_3M, DIR=I
PORT FSL_Clk = "", DIR=I, SIGIS=Clk, BUS=MFSL:SFSL
PORT FSL_Rst = LMB_Rst, DIR=I, BUS=MFSL:SFSL
PORT FSL_S_Clk = FSL_S_Clk, DIR=O, SIGIS=Clk, BUS=SFSL
PORT FSL_S_Read = FSL_S_Read, DIR=O, BUS=SFSL
PORT FSL_S_Data = FSL_S_Data, DIR=I, VEC=[0:31], BUS=SFSL
PORT FSL_S_Control = FSL_S_Control, DIR=O, BUS=SFSL
PORT FSL_S_Exists = FSL_S_Exists, DIR=I, BUS=SFSL
PORT FSL_M_Clk = FSL_M_Clk, DIR=O, SIGIS=Clk, BUS=MFSL
PORT FSL_M_Write = FSL_M_Write, DIR=O, BUS=MFSL
PORT FSL_M_Data = FSL_M_Data, DIR=O, VEC=[0:31], BUS=MFSL
PORT FSL_M_Control = FSL_M_Control, DIR=O, BUS=MFSL
PORT FSL_M_Full = FSL_M_Full, DIR=I, BUS=MFSL

END