Boot ROM, monitor and CP/M for more classic style systems

This tree is intended to provide an alternative boot monitor and management
to the one included with these systems today. The goals are

- Fit happily into an 8K ROM (currently just over 4K)
- Support CP/M 3 and in a way that keeps the speed advantages
- Use the fact the ROM can be banked in and out to maximise the TPA
- Put the BIOS as far as possible in ROM so we have one CP/M for a lot of
  systems
- Support a lot more hardware
	- 16550A serial, SIO and ACIA with autodetect
	- CF adapter or PPIDE with autodetect
	- TMS991A video and PS/2 keyboard for 'home computer' formats
	  (again with autodetect)
	- Eventually hopefully also 26C92 and QUART
	- Have enough ROM space to also support SD card bit bang later on
- Reduce the number of variants by having one ROM and CP/M for all combinations
- Give the user sensible diagnostics. We print a first 'R' very early to help
  debugging boards, and we print a message rather than bombing if the user has
  paged RAM and forgot the extra link wire/80pin connector bits
- Can run without interrupts
- Does not blow away the ROM services when you boot from disk

Compared with SCM right now it is

- Very untested
- Very buggy
- Does not support baud rate changing
- Does not support the diagnostic LED card

This is not yet intended to be used for anything real!


SCM also uses space for things that probably can't be fitted in or don't really
make sense in "Get to CP/M" BIOS mindset. They are trying to solve different
problems thus SCM has

- Z80 assembler
- Z80 disassembler
- Single step
- Register dump
- Switching I/O device
- Timers

The API is very different. This ROM tries to present a CP/M 3 BIOS
interface to the world so has disk support. It also boots in a way that
allows a booted OS to use the BIOS services with a tiny banked BIOS and large
TPA.


Commands

B d			:		attempt a disk boot
G XXXX			:		jump to address
I XXXX			:		display an I/O port value
O XXXX XX		:		write to an I/O port
R XXXX			:		read memory
W XXXX XX		:		write a byte to memory
X XXXX			:		load to XXXX via xmodem (not yet
					completed)

[Note CP/M right now only supports booting off drive C as ldrbios has not
 been updated]

Works on emulator testing
-------------------------
16x50 UART and basic monitor commands
ACIA and basic monitor commands
SIO and basic monitor commands
Detection of classic, 512K/512K, SC108 and SC114 systems
Detection and reporting on non-working paging
Loading and running CP/M
Loading and running legacy CP/M 2.2 images

Untested/incomplete and is still being brought up
-------------------------------------------------
TMS9918A console with ADM3A emulation
PS/2 keyboard interface
XModem

Things to do (other than debug)
-------------------------------
Probe for second 16550A at 0xA8 and assign as AUX
SC26C92/886C81/QUART support
Final disk layout. Right now we use the 256x512 sector trick so that we
have to do no maths on layout. Might be better to be ROMWBW compatible ?
(no - ROMWBW layout is horrible and limiting, better to go to partitions too)
Maybe a separate load binary from a Fuzix fs helper ?
RTC support

Longer Term
-----------
See if we can also support Tom's SBC and Linc80 in the same image
SD card bitbang
Floppy disk
Z80 DMA for CF ? (silly but easy to add)
Maybe disassembler/single step/regdump (probably costs about 1.5K)

CP/M 2.2
--------
The CP/M 2.2 and 3 BIOS are very similar. The DPH and DPB are different but
are not (currently) in the ROM anyway due to GENCPM
ROM SELDSK will behave as CP/M 2.2 wants

SETSEC will need changing as CP/M 2.2 needs 128 byte sectors.
READ and WRITE will need to deblock using the CP/M ROM calls


Memory Layout
-------------
0000-1FFF		ROM
2000-7FFF		Unused (may be paged ROM or RAM)
8000-FDFF		Only used by monitor (can be reused by OS)
			B loads code at 8100h from the boot sectors 2-n
FE00-FEFF		Variables and support code
FF00-FFFF		Function jumps and ROM paging stack

The defined part of the variables area is

FE00		jump to routine to page in ROM. Do not call from below
		8000h or with the stack low. Only affects A.
FE03		jump to routine to page out the ROM. Only affects A.
FE06		call ROM routine in IX. No other registers affected. Not
		re-entrant. Handles all the stack switching itself.

FE00/FE03 pairs must be balanced and do not nest. They may in fact merely
toggle the ROM!

FF00-FF5F	CP/M jump vectors from WBOOT unwards

These must be called with the ROM paged in but the disk routines will page
the ROM out and back in for I/O. SELDSK must be wrapped and DRVTBL must be
provided solely by the BIOS with CP/M itself to keep the system generation
happy (it looks at those tables itself)

FF60-FFFF	Stack