5-Stage-RISC-V-Processor-by-Verilog-HDL

在学习Verilog和Risc-V过程中，利用Verilog编写的RISC-V程序，仅作交流

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
README.md		README.md
RV32I_decode.v		RV32I_decode.v
alu.v		alu.v
branch.v		branch.v
data_mem.v		data_mem.v
defines.v		defines.v
ex.v		ex.v
ex_mem.v		ex_mem.v
id.v		id.v
id_ex.v		id_ex.v
if_id.v		if_id.v
ifetch.v		ifetch.v
imm.v		imm.v
mem.v		mem.v
mem_wb.v		mem_wb.v
mux.v		mux.v
pcreg.v		pcreg.v
risc_v_data.txt		risc_v_data.txt
risc_v_reg.v		risc_v_reg.v
rom.v		rom.v
test_data_input.txt		test_data_input.txt
testbench_if_ex.v		testbench_if_ex.v
testbench_if_id.v		testbench_if_id.v
testbench_risc_v.v		testbench_risc_v.v
top_if_ex.v		top_if_ex.v
top_if_id.v		top_if_id.v
top_risc_v.v		top_risc_v.v
wb.v		wb.v

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