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Setup Verilator for multiple clock domain simulations #176

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JulianKemmerer opened this issue Sep 16, 2023 · 0 comments
Open

Setup Verilator for multiple clock domain simulations #176

JulianKemmerer opened this issue Sep 16, 2023 · 0 comments
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enhancement New feature or request

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@JulianKemmerer
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  • Requires a VHDL async "AXIS style FWFT" fifo implementation to use
    • Real hardware uses manufacturer macros
    • Previously took sync Verilog fifo and used that
  • Simulation should ideally generate clocks in the HDL
    • Ugh oh - how to get that through yosys for write_verilog?
    • GHDL for VHDL to Verilog has duplicate wire issue so can't use that yet
@JulianKemmerer JulianKemmerer added the enhancement New feature or request label Sep 16, 2023
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