Cannot synthesize with Vivado

[franktaTian]

Hi,
I've tried to sythesize vroom design using Vivado.But there are many strange errors .
My flow is ：
1、make fvv generate full set sv and It can run dhrystone.
2、read all sv file into Vivado : the related verilog defines are set just like verilator
Again , can you release the AWS fpga flow and scripts ?
Thanks.

[MoonbaseOtago]

Sorry - I don't really follow this part of github much - I'm afraid the current design is far too big to build on AWS VU09s these days even if it is cut down, I'm waiting for bitcoin to crash so I can afford to buy some bigger cards (VU13s) :-)

The AWS scripts will not work on the current design as so much has changed and also it contains a chunk of code that is Amazon's intellectual property, OK to use on their hardware but I'm afraid I can't just release that externally - sorry