From 20f413aba87c3de35fdf9a711753966eba0b6f91 Mon Sep 17 00:00:00 2001 From: wangyanwen Date: Sat, 29 Jun 2024 23:14:01 +0800 Subject: [PATCH] Revert "dlink include riscv_encoding.h" This reverts commit 963032321bb724fb8fec7c552b0535cf119d3b1f. --- arch/riscv/include/encoding.h | 713 ++++++++++++++++++++++---- arch/riscv/source/riscv-target.c | 281 +++++----- server/gdb-server/source/gdb-server.c | 17 +- 3 files changed, 751 insertions(+), 260 deletions(-) diff --git a/arch/riscv/include/encoding.h b/arch/riscv/include/encoding.h index fcaa3b2..6b911f3 100644 --- a/arch/riscv/include/encoding.h +++ b/arch/riscv/include/encoding.h @@ -1,9 +1,31 @@ -#ifndef __ENCODING_H__ -#define __ENCODING_H__ -#ifdef __cplusplus - extern "C" { -#endif +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_UBE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_VS 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS_SBE 0x0000001000000000 +#define MSTATUS_MBE 0x0000002000000000 +#define MSTATUS_GVA 0x0000004000000000 +#define MSTATUS_MPV 0x0000008000000000 +#define MSTATUS64_SD 0x8000000000000000 #define MATCH_ADD 0x33 #define MASK_ADD 0xfe00707f @@ -2404,108 +2426,579 @@ #define MATCH_ZUNPKD832 0xad700077 #define MASK_ZUNPKD832 0xfff0707f -#define CSR_ZERO (0) -#define CSR_RA (1) -#define CSR_SP (2) -#define CSR_GP (3) -#define CSR_TP (4) -#define CSR_T0 (5) -#define CSR_T1 (6) -#define CSR_T2 (7) -#define CSR_FP (8) -#define CSR_S1 (9) -#define CSR_A0 (10) -#define CSR_A1 (11) -#define CSR_A2 (12) -#define CSR_A3 (13) -#define CSR_A4 (14) -#define CSR_A5 (15) -#define CSR_A6 (16) -#define CSR_A7 (17) -#define CSR_S2 (18) -#define CSR_S3 (19) -#define CSR_S4 (20) -#define CSR_S5 (21) -#define CSR_S6 (22) -#define CSR_S7 (23) -#define CSR_S8 (24) -#define CSR_S9 (25) -#define CSR_S10 (26) -#define CSR_S11 (27) -#define CSR_T3 (28) -#define CSR_T4 (29) -#define CSR_T5 (30) -#define CSR_T6 (31) -#define CSR_PC (32) -#define CSR_FT0 (33) -#define CSR_FT1 (34) -#define CSR_FT2 (35) -#define CSR_FT3 (36) -#define CSR_FT4 (37) -#define CSR_FT5 (38) -#define CSR_FT6 (39) -#define CSR_FT7 (40) -#define CSR_FS0 (41) -#define CSR_FS1 (42) -#define CSR_FA0 (43) -#define CSR_FA1 (44) -#define CSR_FA2 (45) -#define CSR_FA3 (46) -#define CSR_FA4 (47) -#define CSR_FA5 (48) -#define CSR_FA6 (49) -#define CSR_FA7 (50) -#define CSR_FS2 (51) -#define CSR_FS3 (52) -#define CSR_FS4 (53) -#define CSR_FS5 (54) -#define CSR_FS6 (55) -#define CSR_FS7 (56) -#define CSR_FS8 (57) -#define CSR_FS9 (58) -#define CSR_FS10 (59) -#define CSR_FS11 (60) -#define CSR_FT8 (61) -#define CSR_FT9 (62) -#define CSR_FT10 (63) -#define CSR_FT11 (64) -#define CSR_CSR0 (65) -#define CSR_PRIV (4161) -#define CSR_V0 (4162) -#define CSR_V1 (4163) -#define CSR_V2 (4164) -#define CSR_V3 (4165) -#define CSR_V4 (4166) -#define CSR_V5 (4167) -#define CSR_V6 (4168) -#define CSR_V7 (4169) -#define CSR_V8 (4170) -#define CSR_V9 (4171) -#define CSR_V10 (4172) -#define CSR_V11 (4173) -#define CSR_V12 (4174) -#define CSR_V13 (4175) -#define CSR_V14 (4176) -#define CSR_V15 (4177) -#define CSR_V16 (4178) -#define CSR_V17 (4179) -#define CSR_V18 (4181) -#define CSR_V19 (4182) -#define CSR_V20 (4182) -#define CSR_V21 (4183) -#define CSR_V22 (4184) -#define CSR_V23 (4185) -#define CSR_V24 (4186) -#define CSR_V25 (4187) -#define CSR_V26 (4188) -#define CSR_V27 (4189) -#define CSR_V28 (4190) -#define CSR_V29 (4191) -#define CSR_V30 (4192) -#define CSR_V31 (4193) - -#ifdef __cplusplus -} -#endif - -#endif /* __ENCODING_H__ */ \ No newline at end of file +#define RV_REG_ZERO (0) +#define RV_REG_RA (1) +#define RV_REG_SP (2) +#define RV_REG_GP (3) +#define RV_REG_TP (4) +#define RV_REG_T0 (5) +#define RV_REG_T1 (6) +#define RV_REG_T2 (7) +#define RV_REG_FP (8) +#define RV_REG_S1 (9) +#define RV_REG_A0 (10) +#define RV_REG_A1 (11) +#define RV_REG_A2 (12) +#define RV_REG_A3 (13) +#define RV_REG_A4 (14) +#define RV_REG_A5 (15) +#define RV_REG_A6 (16) +#define RV_REG_A7 (17) +#define RV_REG_S2 (18) +#define RV_REG_S3 (19) +#define RV_REG_S4 (20) +#define RV_REG_S5 (21) +#define RV_REG_S6 (22) +#define RV_REG_S7 (23) +#define RV_REG_S8 (24) +#define RV_REG_S9 (25) +#define RV_REG_S10 (26) +#define RV_REG_S11 (27) +#define RV_REG_T3 (28) +#define RV_REG_T4 (29) +#define RV_REG_T5 (30) +#define RV_REG_T6 (31) +#define RV_REG_PC (32) +#define RV_REG_FT0 (33) +#define RV_REG_FT1 (34) +#define RV_REG_FT2 (35) +#define RV_REG_FT3 (36) +#define RV_REG_FT4 (37) +#define RV_REG_FT5 (38) +#define RV_REG_FT6 (39) +#define RV_REG_FT7 (40) +#define RV_REG_FS0 (41) +#define RV_REG_FS1 (42) +#define RV_REG_FA0 (43) +#define RV_REG_FA1 (44) +#define RV_REG_FA2 (45) +#define RV_REG_FA3 (46) +#define RV_REG_FA4 (47) +#define RV_REG_FA5 (48) +#define RV_REG_FA6 (49) +#define RV_REG_FA7 (50) +#define RV_REG_FS2 (51) +#define RV_REG_FS3 (52) +#define RV_REG_FS4 (53) +#define RV_REG_FS5 (54) +#define RV_REG_FS6 (55) +#define RV_REG_FS7 (56) +#define RV_REG_FS8 (57) +#define RV_REG_FS9 (58) +#define RV_REG_FS10 (59) +#define RV_REG_FS11 (60) +#define RV_REG_FT8 (61) +#define RV_REG_FT9 (62) +#define RV_REG_FT10 (63) +#define RV_REG_FT11 (64) +#define RV_REG_CSR0 (65) +#define RV_REG_FFLAGS (65+0x1) +#define RV_REG_FRM (65+0x2) +#define RV_REG_FCSR (65+0x3) +#define RV_REG_UTVT (65+0x7) +#define RV_REG_VSTART (65+0x8) +#define RV_REG_VXSAT (65+0x9) +#define RV_REG_VXRM (65+0xa) +#define RV_REG_VCSR (65+0xf) +#define RV_REG_SEED (65+0x15) +#define RV_REG_UNXTI (65+0x45) +#define RV_REG_UINTSTATUS (65+0x46) +#define RV_REG_USCRATCHCSW (65+0x48) +#define RV_REG_USCRATCHCSWL (65+0x49) +#define RV_REG_SSTATUS (65+0x100) +#define RV_REG_SEDELEG (65+0x102) +#define RV_REG_SIDELEG (65+0x103) +#define RV_REG_SIE (65+0x104) +#define RV_REG_STVEC (65+0x105) +#define RV_REG_SCOUNTEREN (65+0x106) +#define RV_REG_STVT (65+0x107) +#define RV_REG_SENVCFG (65+0x10a) +#define RV_REG_SSTATEEN0 (65+0x10c) +#define RV_REG_SSTATEEN1 (65+0x10d) +#define RV_REG_SSTATEEN2 (65+0x10e) +#define RV_REG_SSTATEEN3 (65+0x10f) +#define RV_REG_SSCRATCH (65+0x140) +#define RV_REG_SEPC (65+0x141) +#define RV_REG_SCAUSE (65+0x142) +#define RV_REG_STVAL (65+0x143) +#define RV_REG_SIP (65+0x144) +#define RV_REG_SNXTI (65+0x145) +#define RV_REG_SINTSTATUS (65+0x146) +#define RV_REG_SSCRATCHCSW (65+0x148) +#define RV_REG_SSCRATCHCSWL (65+0x149) +#define RV_REG_STIMECMP (65+0x14d) +#define RV_REG_STIMECMPH (65+0x15d) +#define RV_REG_SATP (65+0x180) +#define RV_REG_SPMPCFG0 (65+0x1a0) +#define RV_REG_SPMPCFG1 (65+0x1a1) +#define RV_REG_SPMPCFG2 (65+0x1a2) +#define RV_REG_SPMPCFG3 (65+0x1a3) +#define RV_REG_SPMPADDR0 (65+0x1b0) +#define RV_REG_SPMPADDR1 (65+0x1b1) +#define RV_REG_SPMPADDR2 (65+0x1b2) +#define RV_REG_SPMPADDR3 (65+0x1b3) +#define RV_REG_SPMPADDR4 (65+0x1b4) +#define RV_REG_SPMPADDR5 (65+0x1b5) +#define RV_REG_SPMPADDR6 (65+0x1b6) +#define RV_REG_SPMPADDR7 (65+0x1b7) +#define RV_REG_SPMPADDR8 (65+0x1b8) +#define RV_REG_SPMPADDR9 (65+0x1b9) +#define RV_REG_SPMPADDR10 (65+0x1ba) +#define RV_REG_SPMPADDR11 (65+0x1bb) +#define RV_REG_SPMPADDR12 (65+0x1bc) +#define RV_REG_SPMPADDR13 (65+0x1bd) +#define RV_REG_SPMPADDR14 (65+0x1be) +#define RV_REG_SPMPADDR15 (65+0x1bf) +#define RV_REG_VSSTATUS (65+0x200) +#define RV_REG_VSIE (65+0x204) +#define RV_REG_VSTVEC (65+0x205) +#define RV_REG_VSSCRATCH (65+0x240) +#define RV_REG_VSEPC (65+0x241) +#define RV_REG_VSCAUSE (65+0x242) +#define RV_REG_VSTVAL (65+0x243) +#define RV_REG_VSIP (65+0x244) +#define RV_REG_VSTIMECMP (65+0x24d) +#define RV_REG_VSTIMECMPH (65+0x25d) +#define RV_REG_VSATP (65+0x280) +#define RV_REG_MSTATUS (65+0x300) +#define RV_REG_MISA (65+0x301) +#define RV_REG_MEDELEG (65+0x302) +#define RV_REG_MIDELEG (65+0x303) +#define RV_REG_MIE (65+0x304) +#define RV_REG_MTVEC (65+0x305) +#define RV_REG_MCOUNTEREN (65+0x306) +#define RV_REG_MTVT (65+0x307) +#define RV_REG_MENVCFG (65+0x30a) +#define RV_REG_MSTATEEN0 (65+0x30c) +#define RV_REG_MSTATEEN1 (65+0x30d) +#define RV_REG_MSTATEEN2 (65+0x30e) +#define RV_REG_MSTATEEN3 (65+0x30f) +#define RV_REG_MSTATUSH (65+0x310) +#define RV_REG_MENVCFGH (65+0x31a) +#define RV_REG_MSTATEEN0H (65+0x31c) +#define RV_REG_MSTATEEN1H (65+0x31d) +#define RV_REG_MSTATEEN2H (65+0x31e) +#define RV_REG_MSTATEEN3H (65+0x31f) +#define RV_REG_MCOUNTINHIBIT (65+0x320) +#define RV_REG_MHPMEVENT3 (65+0x323) +#define RV_REG_MHPMEVENT4 (65+0x324) +#define RV_REG_MHPMEVENT5 (65+0x325) +#define RV_REG_MHPMEVENT6 (65+0x326) +#define RV_REG_MHPMEVENT7 (65+0x327) +#define RV_REG_MHPMEVENT8 (65+0x328) +#define RV_REG_MHPMEVENT9 (65+0x329) +#define RV_REG_MHPMEVENT10 (65+0x32a) +#define RV_REG_MHPMEVENT11 (65+0x32b) +#define RV_REG_MHPMEVENT12 (65+0x32c) +#define RV_REG_MHPMEVENT13 (65+0x32d) +#define RV_REG_MHPMEVENT14 (65+0x32e) +#define RV_REG_MHPMEVENT15 (65+0x32f) +#define RV_REG_MHPMEVENT16 (65+0x330) +#define RV_REG_MHPMEVENT17 (65+0x331) +#define RV_REG_MHPMEVENT18 (65+0x332) +#define RV_REG_MHPMEVENT19 (65+0x333) +#define RV_REG_MHPMEVENT20 (65+0x334) +#define RV_REG_MHPMEVENT21 (65+0x335) +#define RV_REG_MHPMEVENT22 (65+0x336) +#define RV_REG_MHPMEVENT23 (65+0x337) +#define RV_REG_MHPMEVENT24 (65+0x338) +#define RV_REG_MHPMEVENT25 (65+0x339) +#define RV_REG_MHPMEVENT26 (65+0x33a) +#define RV_REG_MHPMEVENT27 (65+0x33b) +#define RV_REG_MHPMEVENT28 (65+0x33c) +#define RV_REG_MHPMEVENT29 (65+0x33d) +#define RV_REG_MHPMEVENT30 (65+0x33e) +#define RV_REG_MHPMEVENT31 (65+0x33f) +#define RV_REG_MSCRATCH (65+0x340) +#define RV_REG_MEPC (65+0x341) +#define RV_REG_MCAUSE (65+0x342) +#define RV_REG_MTVAL (65+0x343) +#define RV_REG_MIP (65+0x344) +#define RV_REG_MNXTI (65+0x345) +#define RV_REG_MINTSTATUS (65+0x346) +#define RV_REG_MSCRATCHCSW (65+0x348) +#define RV_REG_MSCRATCHCSWL (65+0x349) +#define RV_REG_MTINST (65+0x34a) +#define RV_REG_MTVAL2 (65+0x34b) +#define RV_REG_MCLICBASE (65+0x350) +#define RV_REG_PMPCFG0 (65+0x3a0) +#define RV_REG_PMPCFG1 (65+0x3a1) +#define RV_REG_PMPCFG2 (65+0x3a2) +#define RV_REG_PMPCFG3 (65+0x3a3) +#define RV_REG_PMPCFG4 (65+0x3a4) +#define RV_REG_PMPCFG5 (65+0x3a5) +#define RV_REG_PMPCFG6 (65+0x3a6) +#define RV_REG_PMPCFG7 (65+0x3a7) +#define RV_REG_PMPCFG8 (65+0x3a8) +#define RV_REG_PMPCFG9 (65+0x3a9) +#define RV_REG_PMPCFG10 (65+0x3aa) +#define RV_REG_PMPCFG11 (65+0x3ab) +#define RV_REG_PMPCFG12 (65+0x3ac) +#define RV_REG_PMPCFG13 (65+0x3ad) +#define RV_REG_PMPCFG14 (65+0x3ae) +#define RV_REG_PMPCFG15 (65+0x3af) +#define RV_REG_PMPADDR0 (65+0x3b0) +#define RV_REG_PMPADDR1 (65+0x3b1) +#define RV_REG_PMPADDR2 (65+0x3b2) +#define RV_REG_PMPADDR3 (65+0x3b3) +#define RV_REG_PMPADDR4 (65+0x3b4) +#define RV_REG_PMPADDR5 (65+0x3b5) +#define RV_REG_PMPADDR6 (65+0x3b6) +#define RV_REG_PMPADDR7 (65+0x3b7) +#define RV_REG_PMPADDR8 (65+0x3b8) +#define RV_REG_PMPADDR9 (65+0x3b9) +#define RV_REG_PMPADDR10 (65+0x3ba) +#define RV_REG_PMPADDR11 (65+0x3bb) +#define RV_REG_PMPADDR12 (65+0x3bc) +#define RV_REG_PMPADDR13 (65+0x3bd) +#define RV_REG_PMPADDR14 (65+0x3be) +#define RV_REG_PMPADDR15 (65+0x3bf) +#define RV_REG_PMPADDR16 (65+0x3c0) +#define RV_REG_PMPADDR17 (65+0x3c1) +#define RV_REG_PMPADDR18 (65+0x3c2) +#define RV_REG_PMPADDR19 (65+0x3c3) +#define RV_REG_PMPADDR20 (65+0x3c4) +#define RV_REG_PMPADDR21 (65+0x3c5) +#define RV_REG_PMPADDR22 (65+0x3c6) +#define RV_REG_PMPADDR23 (65+0x3c7) +#define RV_REG_PMPADDR24 (65+0x3c8) +#define RV_REG_PMPADDR25 (65+0x3c9) +#define RV_REG_PMPADDR26 (65+0x3ca) +#define RV_REG_PMPADDR27 (65+0x3cb) +#define RV_REG_PMPADDR28 (65+0x3cc) +#define RV_REG_PMPADDR29 (65+0x3cd) +#define RV_REG_PMPADDR30 (65+0x3ce) +#define RV_REG_PMPADDR31 (65+0x3cf) +#define RV_REG_PMPADDR32 (65+0x3d0) +#define RV_REG_PMPADDR33 (65+0x3d1) +#define RV_REG_PMPADDR34 (65+0x3d2) +#define RV_REG_PMPADDR35 (65+0x3d3) +#define RV_REG_PMPADDR36 (65+0x3d4) +#define RV_REG_PMPADDR37 (65+0x3d5) +#define RV_REG_PMPADDR38 (65+0x3d6) +#define RV_REG_PMPADDR39 (65+0x3d7) +#define RV_REG_PMPADDR40 (65+0x3d8) +#define RV_REG_PMPADDR41 (65+0x3d9) +#define RV_REG_PMPADDR42 (65+0x3da) +#define RV_REG_PMPADDR43 (65+0x3db) +#define RV_REG_PMPADDR44 (65+0x3dc) +#define RV_REG_PMPADDR45 (65+0x3dd) +#define RV_REG_PMPADDR46 (65+0x3de) +#define RV_REG_PMPADDR47 (65+0x3df) +#define RV_REG_PMPADDR48 (65+0x3e0) +#define RV_REG_PMPADDR49 (65+0x3e1) +#define RV_REG_PMPADDR50 (65+0x3e2) +#define RV_REG_PMPADDR51 (65+0x3e3) +#define RV_REG_PMPADDR52 (65+0x3e4) +#define RV_REG_PMPADDR53 (65+0x3e5) +#define RV_REG_PMPADDR54 (65+0x3e6) +#define RV_REG_PMPADDR55 (65+0x3e7) +#define RV_REG_PMPADDR56 (65+0x3e8) +#define RV_REG_PMPADDR57 (65+0x3e9) +#define RV_REG_PMPADDR58 (65+0x3ea) +#define RV_REG_PMPADDR59 (65+0x3eb) +#define RV_REG_PMPADDR60 (65+0x3ec) +#define RV_REG_PMPADDR61 (65+0x3ed) +#define RV_REG_PMPADDR62 (65+0x3ee) +#define RV_REG_PMPADDR63 (65+0x3ef) +#define RV_REG_CCM_UBEGINADDR (65+0x4cb) +#define RV_REG_CCM_UCOMMAND (65+0x4cc) +#define RV_REG_CCM_UDATA (65+0x4cd) +#define RV_REG_CCM_FPIPE (65+0x4cf) +#define RV_REG_SCONTEXT (65+0x5a8) +#define RV_REG_CCM_SBEGINADDR (65+0x5cb) +#define RV_REG_CCM_SCOMMAND (65+0x5cc) +#define RV_REG_CCM_SDATA (65+0x5cd) +#define RV_REG_HSTATUS (65+0x600) +#define RV_REG_HEDELEG (65+0x602) +#define RV_REG_HIDELEG (65+0x603) +#define RV_REG_HIE (65+0x604) +#define RV_REG_HTIMEDELTA (65+0x605) +#define RV_REG_HCOUNTEREN (65+0x606) +#define RV_REG_HGEIE (65+0x607) +#define RV_REG_HENVCFG (65+0x60a) +#define RV_REG_HSTATEEN0 (65+0x60c) +#define RV_REG_HSTATEEN1 (65+0x60d) +#define RV_REG_HSTATEEN2 (65+0x60e) +#define RV_REG_HSTATEEN3 (65+0x60f) +#define RV_REG_HTIMEDELTAH (65+0x615) +#define RV_REG_HENVCFGH (65+0x61a) +#define RV_REG_HSTATEEN0H (65+0x61c) +#define RV_REG_HSTATEEN1H (65+0x61d) +#define RV_REG_HSTATEEN2H (65+0x61e) +#define RV_REG_HSTATEEN3H (65+0x61f) +#define RV_REG_HTVAL (65+0x643) +#define RV_REG_HIP (65+0x644) +#define RV_REG_HVIP (65+0x645) +#define RV_REG_HTINST (65+0x64a) +#define RV_REG_HGATP (65+0x680) +#define RV_REG_HCONTEXT (65+0x6a8) +#define RV_REG_MHPMEVENT3H (65+0x723) +#define RV_REG_MHPMEVENT4H (65+0x724) +#define RV_REG_MHPMEVENT5H (65+0x725) +#define RV_REG_MHPMEVENT6H (65+0x726) +#define RV_REG_MHPMEVENT7H (65+0x727) +#define RV_REG_MHPMEVENT8H (65+0x728) +#define RV_REG_MHPMEVENT9H (65+0x729) +#define RV_REG_MHPMEVENT10H (65+0x72a) +#define RV_REG_MHPMEVENT11H (65+0x72b) +#define RV_REG_MHPMEVENT12H (65+0x72c) +#define RV_REG_MHPMEVENT13H (65+0x72d) +#define RV_REG_MHPMEVENT14H (65+0x72e) +#define RV_REG_MHPMEVENT15H (65+0x72f) +#define RV_REG_MHPMEVENT16H (65+0x730) +#define RV_REG_MHPMEVENT17H (65+0x731) +#define RV_REG_MHPMEVENT18H (65+0x732) +#define RV_REG_MHPMEVENT19H (65+0x733) +#define RV_REG_MHPMEVENT20H (65+0x734) +#define RV_REG_MHPMEVENT21H (65+0x735) +#define RV_REG_MHPMEVENT22H (65+0x736) +#define RV_REG_MHPMEVENT23H (65+0x737) +#define RV_REG_MHPMEVENT24H (65+0x738) +#define RV_REG_MHPMEVENT25H (65+0x739) +#define RV_REG_MHPMEVENT26H (65+0x73a) +#define RV_REG_MHPMEVENT27H (65+0x73b) +#define RV_REG_MHPMEVENT28H (65+0x73c) +#define RV_REG_MHPMEVENT29H (65+0x73d) +#define RV_REG_MHPMEVENT30H (65+0x73e) +#define RV_REG_MHPMEVENT31H (65+0x73f) +#define RV_REG_MSECCFG (65+0x747) +#define RV_REG_MSECCFGH (65+0x757) +#define RV_REG_TSELECT (65+0x7a0) +#define RV_REG_TDATA1 (65+0x7a1) +#define RV_REG_TDATA2 (65+0x7a2) +#define RV_REG_TDATA3 (65+0x7a3) +#define RV_REG_TINFO (65+0x7a4) +#define RV_REG_TCONTROL (65+0x7a5) +#define RV_REG_MCONTEXT (65+0x7a8) +#define RV_REG_MSCONTEXT (65+0x7aa) +#define RV_REG_DCSR (65+0x7b0) +#define RV_REG_DPC (65+0x7b1) +#define RV_REG_DSCRATCH0 (65+0x7b2) +#define RV_REG_DSCRATCH1 (65+0x7b3) +#define RV_REG_MILM_CTL (65+0x7c0) +#define RV_REG_MDLM_CTL (65+0x7c1) +#define RV_REG_MECC_CODE (65+0x7c2) +#define RV_REG_MNVEC (65+0x7c3) +#define RV_REG_MSUBM (65+0x7c4) +#define RV_REG_MDCAUSE (65+0x7c9) +#define RV_REG_MCACHE_CTL (65+0x7ca) +#define RV_REG_CCM_MBEGINADDR (65+0x7cb) +#define RV_REG_CCM_MCOMMAND (65+0x7cc) +#define RV_REG_CCM_MDATA (65+0x7cd) +#define RV_REG_CCM_SUEN (65+0x7ce) +#define RV_REG_MMISC_CTL (65+0x7d0) +#define RV_REG_MSAVESTATUS (65+0x7d6) +#define RV_REG_MSAVEEPC1 (65+0x7d7) +#define RV_REG_MSAVECAUSE1 (65+0x7d8) +#define RV_REG_MSAVEEPC2 (65+0x7d9) +#define RV_REG_MSAVECAUSE2 (65+0x7da) +#define RV_REG_MSAVEDCAUSE1 (65+0x7db) +#define RV_REG_MSAVEDCAUSE2 (65+0x7dc) +#define RV_REG_MTLB_CTL (65+0x7dd) +#define RV_REG_MECC_LOCK (65+0x7de) +#define RV_REG_MFP16MODE (65+0x7e2) +#define RV_REG_LSTEPFORC (65+0x7e9) +#define RV_REG_PUSHMSUBM (65+0x7eb) +#define RV_REG_MTVT2 (65+0x7ec) +#define RV_REG_JALMNXTI (65+0x7ed) +#define RV_REG_PUSHMCAUSE (65+0x7ee) +#define RV_REG_PUSHMEPC (65+0x7ef) +#define RV_REG_MPPICFG_INFO (65+0x7f0) +#define RV_REG_MFIOCFG_INFO (65+0x7f1) +#define RV_REG_MDEVB (65+0x7f3) +#define RV_REG_MDEVM (65+0x7f4) +#define RV_REG_MNOCB (65+0x7f5) +#define RV_REG_MNOCM (65+0x7f6) +#define RV_REG_MIRGB_INFO (65+0x7f7) +#define RV_REG_UCODE (65+0x801) +#define RV_REG_SLEEPVALUE (65+0x811) +#define RV_REG_TXEVT (65+0x812) +#define RV_REG_WFE (65+0x810) +#define RV_REG_JALSNXTI (65+0x947) +#define RV_REG_STVT2 (65+0x948) +#define RV_REG_PUSHSCAUSE (65+0x949) +#define RV_REG_PUSHSEPC (65+0x94a) +#define RV_REG_SDCAUSE (65+0x9c0) +#define RV_REG_MCYCLE (65+0xb00) +#define RV_REG_MINSTRET (65+0xb02) +#define RV_REG_MHPMCOUNTER3 (65+0xb03) +#define RV_REG_MHPMCOUNTER4 (65+0xb04) +#define RV_REG_MHPMCOUNTER5 (65+0xb05) +#define RV_REG_MHPMCOUNTER6 (65+0xb06) +#define RV_REG_MHPMCOUNTER7 (65+0xb07) +#define RV_REG_MHPMCOUNTER8 (65+0xb08) +#define RV_REG_MHPMCOUNTER9 (65+0xb09) +#define RV_REG_MHPMCOUNTER10 (65+0xb0a) +#define RV_REG_MHPMCOUNTER11 (65+0xb0b) +#define RV_REG_MHPMCOUNTER12 (65+0xb0c) +#define RV_REG_MHPMCOUNTER13 (65+0xb0d) +#define RV_REG_MHPMCOUNTER14 (65+0xb0e) +#define RV_REG_MHPMCOUNTER15 (65+0xb0f) +#define RV_REG_MHPMCOUNTER16 (65+0xb10) +#define RV_REG_MHPMCOUNTER17 (65+0xb11) +#define RV_REG_MHPMCOUNTER18 (65+0xb12) +#define RV_REG_MHPMCOUNTER19 (65+0xb13) +#define RV_REG_MHPMCOUNTER20 (65+0xb14) +#define RV_REG_MHPMCOUNTER21 (65+0xb15) +#define RV_REG_MHPMCOUNTER22 (65+0xb16) +#define RV_REG_MHPMCOUNTER23 (65+0xb17) +#define RV_REG_MHPMCOUNTER24 (65+0xb18) +#define RV_REG_MHPMCOUNTER25 (65+0xb19) +#define RV_REG_MHPMCOUNTER26 (65+0xb1a) +#define RV_REG_MHPMCOUNTER27 (65+0xb1b) +#define RV_REG_MHPMCOUNTER28 (65+0xb1c) +#define RV_REG_MHPMCOUNTER29 (65+0xb1d) +#define RV_REG_MHPMCOUNTER30 (65+0xb1e) +#define RV_REG_MHPMCOUNTER31 (65+0xb1f) +#define RV_REG_MCYCLEH (65+0xb80) +#define RV_REG_MINSTRETH (65+0xb82) +#define RV_REG_MHPMCOUNTER3H (65+0xb83) +#define RV_REG_MHPMCOUNTER4H (65+0xb84) +#define RV_REG_MHPMCOUNTER5H (65+0xb85) +#define RV_REG_MHPMCOUNTER6H (65+0xb86) +#define RV_REG_MHPMCOUNTER7H (65+0xb87) +#define RV_REG_MHPMCOUNTER8H (65+0xb88) +#define RV_REG_MHPMCOUNTER9H (65+0xb89) +#define RV_REG_MHPMCOUNTER10H (65+0xb8a) +#define RV_REG_MHPMCOUNTER11H (65+0xb8b) +#define RV_REG_MHPMCOUNTER12H (65+0xb8c) +#define RV_REG_MHPMCOUNTER13H (65+0xb8d) +#define RV_REG_MHPMCOUNTER14H (65+0xb8e) +#define RV_REG_MHPMCOUNTER15H (65+0xb8f) +#define RV_REG_MHPMCOUNTER16H (65+0xb90) +#define RV_REG_MHPMCOUNTER17H (65+0xb91) +#define RV_REG_MHPMCOUNTER18H (65+0xb92) +#define RV_REG_MHPMCOUNTER19H (65+0xb93) +#define RV_REG_MHPMCOUNTER20H (65+0xb94) +#define RV_REG_MHPMCOUNTER21H (65+0xb95) +#define RV_REG_MHPMCOUNTER22H (65+0xb96) +#define RV_REG_MHPMCOUNTER23H (65+0xb97) +#define RV_REG_MHPMCOUNTER24H (65+0xb98) +#define RV_REG_MHPMCOUNTER25H (65+0xb99) +#define RV_REG_MHPMCOUNTER26H (65+0xb9a) +#define RV_REG_MHPMCOUNTER27H (65+0xb9b) +#define RV_REG_MHPMCOUNTER28H (65+0xb9c) +#define RV_REG_MHPMCOUNTER29H (65+0xb9d) +#define RV_REG_MHPMCOUNTER30H (65+0xb9e) +#define RV_REG_MHPMCOUNTER31H (65+0xb9f) +#define RV_REG_IRQCIP (65+0xbd0) +#define RV_REG_IRQCIE (65+0xbd1) +#define RV_REG_IRQCLVL (65+0xbd2) +#define RV_REG_IRQCEDGE (65+0xbd3) +#define RV_REG_IRQCINFO (65+0xbd4) +#define RV_REG_MSIP (65+0xbd8) +#define RV_REG_MTIMECMP (65+0xbd9) +#define RV_REG_MTIME (65+0xbda) +#define RV_REG_MSTOP (65+0xbdb) +#define RV_REG_CYCLE (65+0xc00) +#define RV_REG_TIME (65+0xc01) +#define RV_REG_INSTRET (65+0xc02) +#define RV_REG_HPMCOUNTER3 (65+0xc03) +#define RV_REG_HPMCOUNTER4 (65+0xc04) +#define RV_REG_HPMCOUNTER5 (65+0xc05) +#define RV_REG_HPMCOUNTER6 (65+0xc06) +#define RV_REG_HPMCOUNTER7 (65+0xc07) +#define RV_REG_HPMCOUNTER8 (65+0xc08) +#define RV_REG_HPMCOUNTER9 (65+0xc09) +#define RV_REG_HPMCOUNTER10 (65+0xc0a) +#define RV_REG_HPMCOUNTER11 (65+0xc0b) +#define RV_REG_HPMCOUNTER12 (65+0xc0c) +#define RV_REG_HPMCOUNTER13 (65+0xc0d) +#define RV_REG_HPMCOUNTER14 (65+0xc0e) +#define RV_REG_HPMCOUNTER15 (65+0xc0f) +#define RV_REG_HPMCOUNTER16 (65+0xc10) +#define RV_REG_HPMCOUNTER17 (65+0xc11) +#define RV_REG_HPMCOUNTER18 (65+0xc12) +#define RV_REG_HPMCOUNTER19 (65+0xc13) +#define RV_REG_HPMCOUNTER20 (65+0xc14) +#define RV_REG_HPMCOUNTER21 (65+0xc15) +#define RV_REG_HPMCOUNTER22 (65+0xc16) +#define RV_REG_HPMCOUNTER23 (65+0xc17) +#define RV_REG_HPMCOUNTER24 (65+0xc18) +#define RV_REG_HPMCOUNTER25 (65+0xc19) +#define RV_REG_HPMCOUNTER26 (65+0xc1a) +#define RV_REG_HPMCOUNTER27 (65+0xc1b) +#define RV_REG_HPMCOUNTER28 (65+0xc1c) +#define RV_REG_HPMCOUNTER29 (65+0xc1d) +#define RV_REG_HPMCOUNTER30 (65+0xc1e) +#define RV_REG_HPMCOUNTER31 (65+0xc1f) +#define RV_REG_VL (65+0xc20) +#define RV_REG_VTYPE (65+0xc21) +#define RV_REG_VLENB (65+0xc22) +#define RV_REG_CYCLEH (65+0xc80) +#define RV_REG_TIMEH (65+0xc81) +#define RV_REG_INSTRETH (65+0xc82) +#define RV_REG_HPMCOUNTER3H (65+0xc83) +#define RV_REG_HPMCOUNTER4H (65+0xc84) +#define RV_REG_HPMCOUNTER5H (65+0xc85) +#define RV_REG_HPMCOUNTER6H (65+0xc86) +#define RV_REG_HPMCOUNTER7H (65+0xc87) +#define RV_REG_HPMCOUNTER8H (65+0xc88) +#define RV_REG_HPMCOUNTER9H (65+0xc89) +#define RV_REG_HPMCOUNTER10H (65+0xc8a) +#define RV_REG_HPMCOUNTER11H (65+0xc8b) +#define RV_REG_HPMCOUNTER12H (65+0xc8c) +#define RV_REG_HPMCOUNTER13H (65+0xc8d) +#define RV_REG_HPMCOUNTER14H (65+0xc8e) +#define RV_REG_HPMCOUNTER15H (65+0xc8f) +#define RV_REG_HPMCOUNTER16H (65+0xc90) +#define RV_REG_HPMCOUNTER17H (65+0xc91) +#define RV_REG_HPMCOUNTER18H (65+0xc92) +#define RV_REG_HPMCOUNTER19H (65+0xc93) +#define RV_REG_HPMCOUNTER20H (65+0xc94) +#define RV_REG_HPMCOUNTER21H (65+0xc95) +#define RV_REG_HPMCOUNTER22H (65+0xc96) +#define RV_REG_HPMCOUNTER23H (65+0xc97) +#define RV_REG_HPMCOUNTER24H (65+0xc98) +#define RV_REG_HPMCOUNTER25H (65+0xc99) +#define RV_REG_HPMCOUNTER26H (65+0xc9a) +#define RV_REG_HPMCOUNTER27H (65+0xc9b) +#define RV_REG_HPMCOUNTER28H (65+0xc9c) +#define RV_REG_HPMCOUNTER29H (65+0xc9d) +#define RV_REG_HPMCOUNTER30H (65+0xc9e) +#define RV_REG_HPMCOUNTER31H (65+0xc9f) +#define RV_REG_SCOUNTOVF (65+0xda0) +#define RV_REG_HGEIP (65+0xe12) +#define RV_REG_MVENDORID (65+0xf11) +#define RV_REG_MARCHID (65+0xf12) +#define RV_REG_MIMPID (65+0xf13) +#define RV_REG_MHARTID (65+0xf14) +#define RV_REG_MCONFIGPTR (65+0xf15) +#define RV_REG_MICFG_INFO (65+0xfc0) +#define RV_REG_MDCFG_INFO (65+0xfc1) +#define RV_REG_MCFG_INFO (65+0xfc2) +#define RV_REG_MTLBCFG_INFO (65+0xfc3) +#define RV_REG_PRIV (4161) +#define RV_REG_V0 (4162) +#define RV_REG_V1 (4163) +#define RV_REG_V2 (4164) +#define RV_REG_V3 (4165) +#define RV_REG_V4 (4166) +#define RV_REG_V5 (4167) +#define RV_REG_V6 (4168) +#define RV_REG_V7 (4169) +#define RV_REG_V8 (4170) +#define RV_REG_V9 (4171) +#define RV_REG_V10 (4172) +#define RV_REG_V11 (4173) +#define RV_REG_V12 (4174) +#define RV_REG_V13 (4175) +#define RV_REG_V14 (4176) +#define RV_REG_V15 (4177) +#define RV_REG_V16 (4178) +#define RV_REG_V17 (4179) +#define RV_REG_V18 (4181) +#define RV_REG_V19 (4182) +#define RV_REG_V20 (4182) +#define RV_REG_V21 (4183) +#define RV_REG_V22 (4184) +#define RV_REG_V23 (4185) +#define RV_REG_V24 (4186) +#define RV_REG_V25 (4187) +#define RV_REG_V26 (4188) +#define RV_REG_V27 (4189) +#define RV_REG_V28 (4190) +#define RV_REG_V29 (4191) +#define RV_REG_V30 (4192) +#define RV_REG_V31 (4193) diff --git a/arch/riscv/source/riscv-target.c b/arch/riscv/source/riscv-target.c index e15183d..0582c73 100755 --- a/arch/riscv/source/riscv-target.c +++ b/arch/riscv/source/riscv-target.c @@ -15,7 +15,6 @@ */ #include "riscv-target.h" #include "riscv-tap.h" -#include "riscv_encoding.h" #include "encoding.h" #include "opcodes.h" #include "port.h" @@ -173,41 +172,41 @@ static void rv_dmi_write(uint32_t addr, uint32_t in) static void rv_prep_for_register_access(uint32_t regno) { uint64_t mstatus; - if ((regno >= CSR_FT0) && (regno <= CSR_FT11)) { - rv_target_read_register(&mstatus, CSR_MSTATUS); + if ((regno >= RV_REG_FT0) && (regno <= RV_REG_FT11)) { + rv_target_read_register(&mstatus, RV_REG_MSTATUS); mstatus |= MSTATUS_FS; - rv_target_write_register(&mstatus, CSR_MSTATUS); + rv_target_write_register(&mstatus, RV_REG_MSTATUS); } - if (((regno >= CSR_V0) && (regno <= CSR_V31)) || - ((regno >= CSR_VSTART) && (regno <= CSR_VCSR)) || - ((regno >= CSR_VL) && (regno <= CSR_VLENB))) { - rv_target_read_register(&mstatus, CSR_MSTATUS); + if (((regno >= RV_REG_V0) && (regno <= RV_REG_V31)) || + ((regno >= RV_REG_VSTART) && (regno <= RV_REG_VCSR)) || + ((regno >= RV_REG_VL) && (regno <= RV_REG_VLENB))) { + rv_target_read_register(&mstatus, RV_REG_MSTATUS); mstatus |= MSTATUS_VS; - rv_target_write_register(&mstatus, CSR_MSTATUS); + rv_target_write_register(&mstatus, RV_REG_MSTATUS); } } static void rv_cleanup_after_register_access(uint32_t regno) { uint64_t mstatus; - if ((regno >= CSR_FT0) && (regno <= CSR_FT11)) { - rv_target_read_register(&mstatus, CSR_MSTATUS); + if ((regno >= RV_REG_FT0) && (regno <= RV_REG_FT11)) { + rv_target_read_register(&mstatus, RV_REG_MSTATUS); mstatus &= ~MSTATUS_FS; - rv_target_write_register(&mstatus, CSR_MSTATUS); + rv_target_write_register(&mstatus, RV_REG_MSTATUS); } - if (((regno >= CSR_V0) && (regno <= CSR_V31)) || - ((regno >= CSR_VSTART) && (regno <= CSR_VCSR)) || - ((regno >= CSR_VL) && (regno <= CSR_VLENB))) { - rv_target_read_register(&mstatus, CSR_MSTATUS); + if (((regno >= RV_REG_V0) && (regno <= RV_REG_V31)) || + ((regno >= RV_REG_VSTART) && (regno <= RV_REG_VCSR)) || + ((regno >= RV_REG_VL) && (regno <= RV_REG_VLENB))) { + rv_target_read_register(&mstatus, RV_REG_MSTATUS); mstatus &= ~MSTATUS_VS; - rv_target_write_register(&mstatus, CSR_MSTATUS); + rv_target_write_register(&mstatus, RV_REG_MSTATUS); } } static void rv_register_read(uint32_t *reg, uint32_t regno) { uint32_t mxl; - if (regno == (CSR_DCSR - CSR_CSR0)) { + if (regno == (RV_REG_DCSR - RV_REG_CSR0)) { mxl = MXL_RV32; } else { mxl = target.misa.mxl; @@ -249,7 +248,7 @@ static void rv_register_read(uint32_t *reg, uint32_t regno) static void rv_register_write(uint32_t *reg, uint32_t regno) { uint32_t mxl; - if (regno == (CSR_DCSR - CSR_CSR0)) { + if (regno == (RV_REG_DCSR - RV_REG_CSR0)) { mxl = MXL_RV32; } else { mxl = target.misa.mxl; @@ -430,51 +429,51 @@ static void rv_register_write_buf(void *reg, uint32_t regno) uint32_t inst_num; uint64_t save_fp, save_s1; - rv_target_read_register(&save_fp, CSR_FP); + rv_target_read_register(&save_fp, RV_REG_FP); - if (regno >= CSR_FT0 && regno <= CSR_FT11) { + if (regno >= RV_REG_FT0 && regno <= RV_REG_FT11) { if (target.misa.d && (target.misa.mxl == MXL_RV32)) {// RV32 D uint64_t scratch_addr; rv_dmi_read(RV_DM_HALT_INFO, &target.dm.hartinfo.value); scratch_addr = target.dm.hartinfo.dataaddr; - inst[0] = fld(regno - CSR_FT0, CSR_FP, 0); + inst[0] = fld(regno - RV_REG_FT0, RV_REG_FP, 0); inst_num = 1; - rv_target_write_register(&scratch_addr, CSR_FP); + rv_target_write_register(&scratch_addr, RV_REG_FP); rv_memory_write(reg, scratch_addr, 8, RV_AAMSIZE_32BITS); rv_program_exec(inst, inst_num); } else if (target.misa.d) {// RV64 D - inst[0] = fmv_d_x(regno - CSR_FT0, CSR_FP); + inst[0] = fmv_d_x(regno - RV_REG_FT0, RV_REG_FP); inst_num = 1; - rv_target_write_register(reg, CSR_FP); + rv_target_write_register(reg, RV_REG_FP); rv_program_exec(inst, inst_num); } else {// RV32/RV64 F - inst[0] = fmv_w_x(regno - CSR_FT0, CSR_FP); + inst[0] = fmv_w_x(regno - RV_REG_FT0, RV_REG_FP); inst_num = 1; - rv_target_write_register(reg, CSR_FP); + rv_target_write_register(reg, RV_REG_FP); rv_program_exec(inst, inst_num); } - } else if (regno == CSR_VL) { - rv_target_read_register(&save_s1, CSR_S1); - inst[0] = csrr(CSR_S1, CSR_VTYPE - CSR_CSR0); - inst[1] = vsetvl(CSR_ZERO, CSR_FP, CSR_S1); + } else if (regno == RV_REG_VL) { + rv_target_read_register(&save_s1, RV_REG_S1); + inst[0] = csrr(RV_REG_S1, RV_REG_VTYPE - RV_REG_CSR0); + inst[1] = vsetvl(RV_REG_ZERO, RV_REG_FP, RV_REG_S1); inst_num = 2; - rv_target_write_register(reg, CSR_FP); + rv_target_write_register(reg, RV_REG_FP); rv_program_exec(inst, inst_num); - rv_target_write_register(&save_s1, CSR_S1); - } else if (regno == CSR_VTYPE) { - rv_target_read_register(&save_s1, CSR_S1); - inst[0] = csrr(CSR_S1, CSR_VL - CSR_CSR0); - inst[1] = vsetvl(CSR_ZERO, CSR_S1, CSR_FP); + rv_target_write_register(&save_s1, RV_REG_S1); + } else if (regno == RV_REG_VTYPE) { + rv_target_read_register(&save_s1, RV_REG_S1); + inst[0] = csrr(RV_REG_S1, RV_REG_VL - RV_REG_CSR0); + inst[1] = vsetvl(RV_REG_ZERO, RV_REG_S1, RV_REG_FP); inst_num = 2; - rv_target_write_register(reg, CSR_FP); + rv_target_write_register(reg, RV_REG_FP); rv_program_exec(inst, inst_num); - rv_target_write_register(&save_s1, CSR_S1); - } else if (regno >= CSR_CSR0 && regno <= (4095 + CSR_CSR0)) { - inst[0] = csrrw(CSR_ZERO, CSR_FP, regno - CSR_CSR0); + rv_target_write_register(&save_s1, RV_REG_S1); + } else if (regno >= RV_REG_CSR0 && regno <= (4095 + RV_REG_CSR0)) { + inst[0] = csrrw(RV_REG_ZERO, RV_REG_FP, regno - RV_REG_CSR0); inst_num = 1; - rv_target_write_register(reg, CSR_FP); + rv_target_write_register(reg, RV_REG_FP); rv_program_exec(inst, inst_num); - } else if (CSR_V0 < regno < CSR_V31) { + } else if (RV_REG_V0 < regno < RV_REG_V31) { uint64_t xlen, debug_vl, encoded_vsew; xlen = target.misa.mxl * 32; if (MXL_RV32 == target.misa.mxl) { @@ -483,21 +482,21 @@ static void rv_register_write_buf(void *reg, uint32_t regno) encoded_vsew = 3 << 3; } debug_vl = ((target.vlenb * 8) + xlen - 1) / xlen; - rv_register_write_buf(&encoded_vsew, CSR_VTYPE); - rv_register_write_buf(&debug_vl, CSR_VL); - inst[0] = vslide1down_vx(regno - CSR_V0, regno - CSR_V0, CSR_FP, true); + rv_register_write_buf(&encoded_vsew, RV_REG_VTYPE); + rv_register_write_buf(&debug_vl, RV_REG_VL); + inst[0] = vslide1down_vx(regno - RV_REG_V0, regno - RV_REG_V0, RV_REG_FP, true); inst_num = 1; for (int i = 0; i < debug_vl; i++) { if (MXL_RV32 == target.misa.mxl) { - rv_target_write_register((uint32_t*)reg + i, CSR_FP); + rv_target_write_register((uint32_t*)reg + i, RV_REG_FP); } else if (MXL_RV64 == target.misa.mxl) { - rv_target_write_register((uint64_t*)reg + i, CSR_FP); + rv_target_write_register((uint64_t*)reg + i, RV_REG_FP); } rv_program_exec(inst, inst_num); } } - rv_target_write_register(&save_fp, CSR_FP); + rv_target_write_register(&save_fp, RV_REG_FP); } static void rv_register_read_buf(void *reg, uint32_t regno) @@ -506,35 +505,35 @@ static void rv_register_read_buf(void *reg, uint32_t regno) uint32_t inst_num; uint64_t save_fp; - rv_target_read_register(&save_fp, CSR_FP); + rv_target_read_register(&save_fp, RV_REG_FP); - if (regno >= CSR_FT0 && regno <= CSR_FT11) { + if (regno >= RV_REG_FT0 && regno <= RV_REG_FT11) { if (target.misa.d && (target.misa.mxl == MXL_RV32)) {// RV32 D uint64_t scratch_addr; rv_dmi_read(RV_DM_HALT_INFO, &target.dm.hartinfo.value); scratch_addr = target.dm.hartinfo.dataaddr; - inst[0] = fsd(regno - CSR_FT0, CSR_FP, 0); + inst[0] = fsd(regno - RV_REG_FT0, RV_REG_FP, 0); inst_num = 1; - rv_target_write_register(&scratch_addr, CSR_FP); + rv_target_write_register(&scratch_addr, RV_REG_FP); rv_program_exec(inst, inst_num); rv_memory_read(reg, scratch_addr, 8, RV_AAMSIZE_32BITS); } else if (target.misa.d) {// RV64 D - inst[0] = fmv_x_d(CSR_FP, regno - CSR_FT0); + inst[0] = fmv_x_d(RV_REG_FP, regno - RV_REG_FT0); inst_num = 1; rv_program_exec(inst, inst_num); - rv_target_read_register(reg, CSR_FP); + rv_target_read_register(reg, RV_REG_FP); } else {// RV32/RV64 F - inst[0] = fmv_x_w(CSR_FP, regno - CSR_FT0); + inst[0] = fmv_x_w(RV_REG_FP, regno - RV_REG_FT0); inst_num = 1; rv_program_exec(inst, inst_num); - rv_target_read_register(reg, CSR_FP); + rv_target_read_register(reg, RV_REG_FP); } - } else if (regno >= CSR_CSR0 && regno <= (4095 + CSR_CSR0)) { - inst[0] = csrrs(CSR_FP, CSR_ZERO, regno - CSR_CSR0); + } else if (regno >= RV_REG_CSR0 && regno <= (4095 + RV_REG_CSR0)) { + inst[0] = csrrs(RV_REG_FP, RV_REG_ZERO, regno - RV_REG_CSR0); inst_num = 1; rv_program_exec(inst, inst_num); - rv_target_read_register(reg, CSR_FP); - } else if (CSR_V0 < regno < CSR_V31) { + rv_target_read_register(reg, RV_REG_FP); + } else if (RV_REG_V0 < regno < RV_REG_V31) { uint64_t xlen, debug_vl, encoded_vsew; xlen = target.misa.mxl * 32; if (MXL_RV32 == target.misa.mxl) { @@ -543,36 +542,36 @@ static void rv_register_read_buf(void *reg, uint32_t regno) encoded_vsew = 3 << 3; } debug_vl = ((target.vlenb * 8) + xlen - 1) / xlen; - rv_register_write_buf(&encoded_vsew, CSR_VTYPE); - rv_register_write_buf(&debug_vl, CSR_VL); - inst[0] = vmv_x_s(CSR_FP, regno - CSR_V0); - inst[1] = vslide1down_vx(regno - CSR_V0, regno - CSR_V0, CSR_FP, true); + rv_register_write_buf(&encoded_vsew, RV_REG_VTYPE); + rv_register_write_buf(&debug_vl, RV_REG_VL); + inst[0] = vmv_x_s(RV_REG_FP, regno - RV_REG_V0); + inst[1] = vslide1down_vx(regno - RV_REG_V0, regno - RV_REG_V0, RV_REG_FP, true); inst_num = 2; for (int i = 0; i < debug_vl; i++) { rv_program_exec(inst, inst_num); if (MXL_RV32 == target.misa.mxl) { - rv_target_read_register((uint32_t*)reg + i, CSR_FP); + rv_target_read_register((uint32_t*)reg + i, RV_REG_FP); } else if (MXL_RV64 == target.misa.mxl) { - rv_target_read_register((uint64_t*)reg + i, CSR_FP); + rv_target_read_register((uint64_t*)reg + i, RV_REG_FP); } } } - rv_target_write_register(&save_fp, CSR_FP); + rv_target_write_register(&save_fp, RV_REG_FP); } static void rv_prep_for_vector_access() { //prep for vector access - rv_register_read_buf(&save_vtype, CSR_VTYPE); - rv_register_read_buf(&save_vl, CSR_VL); + rv_register_read_buf(&save_vtype, RV_REG_VTYPE); + rv_register_read_buf(&save_vl, RV_REG_VL); } static void rv_cleanup_for_vector_access() { //cleanup after vector access - rv_register_write_buf(&save_vtype, CSR_VTYPE); - rv_register_write_buf(&save_vl, CSR_VL); + rv_register_write_buf(&save_vtype, RV_REG_VTYPE); + rv_register_write_buf(&save_vl, RV_REG_VL); } static void rv_parse_watchpoint_inst(uint32_t inst, uint32_t* regno, uint32_t* offset) @@ -785,10 +784,10 @@ void rv_target_init_after_halted(rv_target_error_t *err) rv_misa_rv32_t misa32; rv_misa_rv64_t misa64; target.misa.mxl = MXL_RV64; - rv_target_read_register(&misa64, CSR_MISA); + rv_target_read_register(&misa64, RV_REG_MISA); if (err_flag) { target.misa.mxl = MXL_RV32; - rv_target_read_register(&misa32, CSR_MISA); + rv_target_read_register(&misa32, RV_REG_MISA); if (err_flag) { *err = rv_target_error_debug_module; return; @@ -809,12 +808,12 @@ void rv_target_init_after_halted(rv_target_error_t *err) target.misa.mxl = misa64.mxl; } if (target.misa.v) { - rv_target_read_register(&target.vlenb, CSR_VLENB); + rv_target_read_register(&target.vlenb, RV_REG_VLENB); } else { target.vlenb = 0xFFFFFFFF; } - rv_target_read_register(&dcsr.value, CSR_DCSR); + rv_target_read_register(&dcsr.value, RV_REG_DCSR); if (dcsr.xdebugver != 4) { *err = rv_target_error_compat; return; @@ -826,14 +825,14 @@ void rv_target_init_after_halted(rv_target_error_t *err) dcsr.ebreakm = 1; dcsr.ebreaks = 1; dcsr.ebreaku = 1; - rv_target_write_register(&dcsr.value, CSR_DCSR); + rv_target_write_register(&dcsr.value, RV_REG_DCSR); /* * clear all hardware breakpoints */ for(i = 0; i < RV_TARGET_CONFIG_HARDWARE_BREAKPOINT_NUM; i++) { - rv_target_write_register(&i, CSR_TSELECT); - rv_target_write_register(&zero, CSR_TDATA1); + rv_target_write_register(&i, RV_REG_TSELECT); + rv_target_write_register(&zero, RV_REG_TDATA1); } } @@ -842,11 +841,11 @@ void rv_target_fini_pre(void) /* * ebreak instructions in X-mode behave as described in the Privileged Spec. */ - rv_target_read_register(&dcsr.value, CSR_DCSR); + rv_target_read_register(&dcsr.value, RV_REG_DCSR); dcsr.ebreakm = 0; dcsr.ebreaks = 0; dcsr.ebreaku = 0; - rv_target_write_register(&dcsr.value, CSR_DCSR); + rv_target_write_register(&dcsr.value, RV_REG_DCSR); /* * Disable debug module @@ -867,9 +866,9 @@ void rv_target_read_core_registers(void *regs) } } if (MXL_RV32 == target.misa.mxl) { - rv_target_read_register((uint32_t*)regs + 32, CSR_DPC); + rv_target_read_register((uint32_t*)regs + 32, RV_REG_DPC); } else if (MXL_RV64 == target.misa.mxl) { - rv_target_read_register((uint64_t*)regs + 32, CSR_DPC); + rv_target_read_register((uint64_t*)regs + 32, RV_REG_DPC); } } @@ -885,35 +884,35 @@ void rv_target_write_core_registers(void *regs) } } if (MXL_RV32 == target.misa.mxl) { - rv_target_write_register((uint32_t*)regs + 32, CSR_DPC); + rv_target_write_register((uint32_t*)regs + 32, RV_REG_DPC); } else if (MXL_RV64 == target.misa.mxl) { - rv_target_write_register((uint64_t*)regs + 32, CSR_DPC); + rv_target_write_register((uint64_t*)regs + 32, RV_REG_DPC); } } void rv_target_read_register(void *reg, uint32_t regno) { rv_prep_for_register_access(regno); - if (regno >= CSR_ZERO && regno < CSR_PC) { - rv_register_read((uint32_t*)reg, 0x1000 + regno - CSR_ZERO); - } else if (regno == CSR_PC) { - rv_target_read_register(reg, CSR_DPC); - } else if (regno >= CSR_FT0 && regno <= CSR_FT11) { - rv_register_read((uint32_t*)reg, 0x1020 + regno - CSR_FT0); + if (regno >= RV_REG_ZERO && regno < RV_REG_PC) { + rv_register_read((uint32_t*)reg, 0x1000 + regno - RV_REG_ZERO); + } else if (regno == RV_REG_PC) { + rv_target_read_register(reg, RV_REG_DPC); + } else if (regno >= RV_REG_FT0 && regno <= RV_REG_FT11) { + rv_register_read((uint32_t*)reg, 0x1020 + regno - RV_REG_FT0); /* abstract fail try progbuf */ if (err_flag) { rv_register_read_buf(reg, regno); } - } else if (regno >= CSR_CSR0 && regno <= (4095 + CSR_CSR0)) { - rv_register_read((uint32_t*)reg, regno - CSR_CSR0); + } else if (regno >= RV_REG_CSR0 && regno <= (4095 + RV_REG_CSR0)) { + rv_register_read((uint32_t*)reg, regno - RV_REG_CSR0); /* abstract fail try progbuf */ if (err_flag) { rv_register_read_buf(reg, regno); } - } else if (regno == CSR_PRIV) { - rv_target_read_register(&dcsr.value, CSR_DCSR); + } else if (regno == RV_REG_PRIV) { + rv_target_read_register(&dcsr.value, RV_REG_DCSR); *(uint32_t*)reg = dcsr.prv; - } else if (regno >= CSR_V0 && regno <= CSR_V31) { + } else if (regno >= RV_REG_V0 && regno <= RV_REG_V31) { rv_prep_for_vector_access(); rv_register_read_buf(reg, regno); rv_cleanup_for_vector_access(); @@ -926,27 +925,27 @@ void rv_target_read_register(void *reg, uint32_t regno) void rv_target_write_register(void *reg, uint32_t regno) { rv_prep_for_register_access(regno); - if (regno >= CSR_ZERO && regno < CSR_PC) { - rv_register_write((uint32_t*)reg, 0x1000 + regno - CSR_ZERO); - } else if (regno == CSR_PC) { - rv_target_write_register(reg, CSR_DPC); - } else if (regno >= CSR_FT0 && regno <= CSR_FT11) { - rv_register_write((uint32_t*)reg, 0x1020 + regno - CSR_FT0); + if (regno >= RV_REG_ZERO && regno < RV_REG_PC) { + rv_register_write((uint32_t*)reg, 0x1000 + regno - RV_REG_ZERO); + } else if (regno == RV_REG_PC) { + rv_target_write_register(reg, RV_REG_DPC); + } else if (regno >= RV_REG_FT0 && regno <= RV_REG_FT11) { + rv_register_write((uint32_t*)reg, 0x1020 + regno - RV_REG_FT0); /* abstract fail try progbuf */ if (err_flag) { rv_register_write_buf(reg, regno); } - } else if (regno >= CSR_CSR0 && regno <= (4095 + CSR_CSR0)) { - rv_register_write((uint32_t*)reg, regno - CSR_CSR0); + } else if (regno >= RV_REG_CSR0 && regno <= (4095 + RV_REG_CSR0)) { + rv_register_write((uint32_t*)reg, regno - RV_REG_CSR0); /* abstract fail try progbuf */ if (err_flag) { rv_register_write_buf(reg, regno); } - } else if (regno == CSR_PRIV) { - rv_target_read_register(&dcsr.value, CSR_DCSR); + } else if (regno == RV_REG_PRIV) { + rv_target_read_register(&dcsr.value, RV_REG_DCSR); dcsr.prv = *(uint32_t*)reg; - rv_target_write_register(&dcsr.value, CSR_DCSR); - } else if (regno >= CSR_V0 && regno <= CSR_V31) { + rv_target_write_register(&dcsr.value, RV_REG_DCSR); + } else if (regno >= RV_REG_V0 && regno <= RV_REG_V31) { rv_prep_for_vector_access(); rv_register_write_buf(reg, regno); rv_cleanup_for_vector_access(); @@ -1033,23 +1032,23 @@ void rv_target_halt_check(rv_target_halt_info_t* halt_info) rv_dmi_read(RV_DM_DEBUG_MODULE_STATUS, &target.dm.dmstatus.value); if (target.dm.dmstatus.allhalted) { - rv_target_read_register(&dcsr.value, CSR_DCSR); + rv_target_read_register(&dcsr.value, RV_REG_DCSR); if (dcsr.cause == RV_CSR_DCSR_CAUSE_EBREAK) { halt_info->reason = rv_target_halt_reason_software_breakpoint; } else if (dcsr.cause == RV_CSR_DCSR_CAUSE_TRIGGER) { halt_info->reason = rv_target_halt_reason_other; - rv_target_read_register(&tselect, CSR_TSELECT); + rv_target_read_register(&tselect, RV_REG_TSELECT); for(i = 0; i < RV_TARGET_CONFIG_HARDWARE_BREAKPOINT_NUM; i++) { if (hardware_breakpoints[i].type != rv_target_breakpoint_type_unused) { if (MXL_RV32 == target.misa.mxl) { target.tr32.tselect = i; - rv_target_write_register(&target.tr32.tselect, CSR_TSELECT); - rv_target_read_register(&target.tr32.tdata1.value, CSR_TDATA1); + rv_target_write_register(&target.tr32.tselect, RV_REG_TSELECT); + rv_target_read_register(&target.tr32.tdata1.value, RV_REG_TDATA1); mc_hit = target.tr32.tdata1.mc.hit; } if (MXL_RV64 == target.misa.mxl) { target.tr64.tselect = i; - rv_target_write_register((uint32_t*)&target.tr64.tselect, CSR_TSELECT); - rv_target_read_register(&target.tr64.tdata1.value, CSR_TDATA1); + rv_target_write_register((uint32_t*)&target.tr64.tselect, RV_REG_TSELECT); + rv_target_read_register(&target.tr64.tdata1.value, RV_REG_TDATA1); mc_hit = target.tr64.tdata1.mc.hit; } if (mc_hit) { @@ -1071,8 +1070,8 @@ void rv_target_halt_check(rv_target_halt_info_t* halt_info) } } } - rv_target_write_register(&tselect, CSR_TSELECT); - rv_target_read_register(&dpc, CSR_DPC); + rv_target_write_register(&tselect, RV_REG_TSELECT); + rv_target_read_register(&dpc, RV_REG_DPC); for(i = 0; i < RV_TARGET_CONFIG_HARDWARE_BREAKPOINT_NUM; i++) { if (hardware_breakpoints[i].type == rv_target_breakpoint_type_hardware) { if (hardware_breakpoints[i].addr == dpc) { @@ -1129,9 +1128,9 @@ void rv_target_halt_check(rv_target_halt_info_t* halt_info) void rv_target_resume(void) { - rv_target_read_register(&dcsr.value, CSR_DCSR); + rv_target_read_register(&dcsr.value, RV_REG_DCSR); dcsr.step = 0; - rv_target_write_register(&dcsr.value, CSR_DCSR); + rv_target_write_register(&dcsr.value, RV_REG_DCSR); target.dm.dmcontrol.value = 0; target.dm.dmcontrol.resumereq = 1; @@ -1141,9 +1140,9 @@ void rv_target_resume(void) void rv_target_step(void) { - rv_target_read_register(&dcsr.value, CSR_DCSR); + rv_target_read_register(&dcsr.value, RV_REG_DCSR); dcsr.step = 1; - rv_target_write_register(&dcsr.value, CSR_DCSR); + rv_target_write_register(&dcsr.value, RV_REG_DCSR); target.dm.dmcontrol.value = 0; target.dm.dmcontrol.resumereq = 1; @@ -1183,7 +1182,7 @@ void rv_target_insert_breakpoint(rv_target_breakpoint_type_t type, uint64_t addr } else { tselect_rd = 0; tdata1_rd = 0; - rv_target_read_register(&tselect, CSR_TSELECT); + rv_target_read_register(&tselect, RV_REG_TSELECT); for(i = 0; i < RV_TARGET_CONFIG_HARDWARE_BREAKPOINT_NUM; i++) { if (hardware_breakpoints[i].type == rv_target_breakpoint_type_unused) { hardware_breakpoints[i].type = type; @@ -1191,13 +1190,13 @@ void rv_target_insert_breakpoint(rv_target_breakpoint_type_t type, uint64_t addr hardware_breakpoints[i].kind = kind; if (MXL_RV32 == target.misa.mxl) { target.tr32.tselect = i; - rv_target_write_register(&target.tr32.tselect, CSR_TSELECT); - rv_target_read_register(&tselect_rd, CSR_TSELECT); + rv_target_write_register(&target.tr32.tselect, RV_REG_TSELECT); + rv_target_read_register(&tselect_rd, RV_REG_TSELECT); if (target.tr32.tselect != tselect_rd) { *err = 0x0e; return; } - rv_target_read_register(&target.tr32.tdata1.value, CSR_TDATA1); + rv_target_read_register(&target.tr32.tdata1.value, RV_REG_TDATA1); target.tr32.tdata1.mc.dmode = 1; target.tr32.tdata1.mc.action = 1; target.tr32.tdata1.mc.match = 0; @@ -1225,22 +1224,22 @@ void rv_target_insert_breakpoint(rv_target_breakpoint_type_t type, uint64_t addr default: break; } - rv_target_write_register(&target.tr32.tdata1.value, CSR_TDATA1); - rv_target_read_register(&tdata1_rd, CSR_TDATA1); + rv_target_write_register(&target.tr32.tdata1.value, RV_REG_TDATA1); + rv_target_read_register(&tdata1_rd, RV_REG_TDATA1); if (target.tr32.tdata1.value != tdata1_rd) { *err = 0x0e; return; } - rv_target_write_register(&hardware_breakpoints[target.tr32.tselect].addr, CSR_TDATA2); + rv_target_write_register(&hardware_breakpoints[target.tr32.tselect].addr, RV_REG_TDATA2); } else if (MXL_RV64 == target.misa.mxl) { target.tr64.tselect = i; - rv_target_write_register(&target.tr64.tselect, CSR_TSELECT); - rv_target_read_register(&tselect_rd, CSR_TSELECT); + rv_target_write_register(&target.tr64.tselect, RV_REG_TSELECT); + rv_target_read_register(&tselect_rd, RV_REG_TSELECT); if (target.tr64.tselect != tselect_rd) { *err = 0x0e; return; } - rv_target_read_register(&target.tr64.tdata1.value, CSR_TDATA1); + rv_target_read_register(&target.tr64.tdata1.value, RV_REG_TDATA1); target.tr64.tdata1.mc.dmode = 1; target.tr64.tdata1.mc.action = 1; target.tr64.tdata1.mc.match = 0; @@ -1268,18 +1267,18 @@ void rv_target_insert_breakpoint(rv_target_breakpoint_type_t type, uint64_t addr default: break; } - rv_target_write_register(&target.tr64.tdata1.value, CSR_TDATA1); - rv_target_read_register(&tdata1_rd, CSR_TDATA1); + rv_target_write_register(&target.tr64.tdata1.value, RV_REG_TDATA1); + rv_target_read_register(&tdata1_rd, RV_REG_TDATA1); if (target.tr64.tdata1.value != tdata1_rd) { *err = 0x0e; return; } - rv_target_write_register(&hardware_breakpoints[target.tr64.tselect].addr, CSR_TDATA2); + rv_target_write_register(&hardware_breakpoints[target.tr64.tselect].addr, RV_REG_TDATA2); } break; } } - rv_target_write_register(&tselect, CSR_TSELECT); + rv_target_write_register(&tselect, RV_REG_TSELECT); if (i == RV_TARGET_CONFIG_HARDWARE_BREAKPOINT_NUM) { *err = 0x0e; return; @@ -1314,34 +1313,34 @@ void rv_target_remove_breakpoint(rv_target_breakpoint_type_t type, uint64_t addr } } else { tselect_rd = 0; - rv_target_read_register(&tselect, CSR_TSELECT); + rv_target_read_register(&tselect, RV_REG_TSELECT); for(i = 0; i < RV_TARGET_CONFIG_HARDWARE_BREAKPOINT_NUM; i++) { if ((hardware_breakpoints[i].type == type) && (hardware_breakpoints[i].addr == addr) && (hardware_breakpoints[i].kind == kind)) { if (MXL_RV32 == target.misa.mxl) { target.tr32.tselect = i; - rv_target_write_register(&target.tr32.tselect, CSR_TSELECT); - rv_target_read_register(&tselect_rd, CSR_TSELECT); + rv_target_write_register(&target.tr32.tselect, RV_REG_TSELECT); + rv_target_read_register(&tselect_rd, RV_REG_TSELECT); if (target.tr32.tselect != tselect_rd) { *err = 0x0e; return; } } else if (MXL_RV64 == target.misa.mxl) { target.tr64.tselect = i; - rv_target_write_register(&target.tr64.tselect, CSR_TSELECT); - rv_target_read_register(&tselect_rd, CSR_TSELECT); + rv_target_write_register(&target.tr64.tselect, RV_REG_TSELECT); + rv_target_read_register(&tselect_rd, RV_REG_TSELECT); if (target.tr64.tselect != tselect_rd) { *err = 0x0e; return; } } - rv_target_write_register(&zero, CSR_TDATA1); + rv_target_write_register(&zero, RV_REG_TDATA1); hardware_breakpoints[i].type = rv_target_breakpoint_type_unused; break; } } - rv_target_write_register(&tselect, CSR_TSELECT); + rv_target_write_register(&tselect, RV_REG_TSELECT); if (i == RV_TARGET_CONFIG_HARDWARE_BREAKPOINT_NUM) { *err = 0x0e; return; diff --git a/server/gdb-server/source/gdb-server.c b/server/gdb-server/source/gdb-server.c index 3ef2f81..0358f01 100755 --- a/server/gdb-server/source/gdb-server.c +++ b/server/gdb-server/source/gdb-server.c @@ -16,7 +16,6 @@ #include "gdb-packet.h" #include "riscv-target.h" -#include "riscv_encoding.h" #include "encoding.h" #include "flash.h" #include "led.h" @@ -425,7 +424,7 @@ void gdb_server_cmd_p(void) sscanf(&cmd.data[1], "%x", &gdb_server_i.reg_tmp_num); rv_target_read_register(gdb_server_i.reg_tmp, gdb_server_i.reg_tmp_num); - if ((gdb_server_i.reg_tmp_num >= CSR_V0) && (gdb_server_i.reg_tmp_num <= CSR_V31)) { + if ((gdb_server_i.reg_tmp_num >= RV_REG_V0) && (gdb_server_i.reg_tmp_num <= RV_REG_V31)) { uint32_t data_bits = rv_target_vlenb() * 8; uint32_t xlen = rv_target_mxl() * 32; uint32_t debug_vl = (data_bits + xlen - 1) / xlen; @@ -463,7 +462,7 @@ void gdb_server_cmd_P(void) sscanf(&cmd.data[1], "%x", &gdb_server_i.reg_tmp_num); p = strchr(&cmd.data[1], '='); p++; - if ((gdb_server_i.reg_tmp_num >= CSR_V0) && (gdb_server_i.reg_tmp_num <= CSR_V31)) { + if ((gdb_server_i.reg_tmp_num >= RV_REG_V0) && (gdb_server_i.reg_tmp_num <= RV_REG_V31)) { uint32_t data_bits = rv_target_vlenb() * 8; uint32_t xlen = rv_target_mxl() * 32; uint32_t debug_vl = (data_bits + xlen - 1) / xlen; @@ -644,22 +643,22 @@ void gdb_server_cmd_custom_algorithm(const char* data) rv_target_read_core_registers(gdb_server_i.regs); gdb_server_i.restore_reg_flag = true; /* Run algorithm */ - gdb_server_i.reg_tmp_num = CSR_PC; + gdb_server_i.reg_tmp_num = RV_REG_PC; gdb_server_i.reg_tmp[0] = loader_addr; rv_target_write_register(gdb_server_i.reg_tmp, gdb_server_i.reg_tmp_num); - gdb_server_i.reg_tmp_num = CSR_A0; + gdb_server_i.reg_tmp_num = RV_REG_A0; gdb_server_i.reg_tmp[0] = cs; rv_target_write_register(gdb_server_i.reg_tmp, gdb_server_i.reg_tmp_num); - gdb_server_i.reg_tmp_num = CSR_A1; + gdb_server_i.reg_tmp_num = RV_REG_A1; gdb_server_i.reg_tmp[0] = spi_base; rv_target_write_register(gdb_server_i.reg_tmp, gdb_server_i.reg_tmp_num); - gdb_server_i.reg_tmp_num = CSR_A2; + gdb_server_i.reg_tmp_num = RV_REG_A2; gdb_server_i.reg_tmp[0] = params1; rv_target_write_register(gdb_server_i.reg_tmp, gdb_server_i.reg_tmp_num); - gdb_server_i.reg_tmp_num = CSR_A3; + gdb_server_i.reg_tmp_num = RV_REG_A3; gdb_server_i.reg_tmp[0] = params2; rv_target_write_register(gdb_server_i.reg_tmp, gdb_server_i.reg_tmp_num); - gdb_server_i.reg_tmp_num = CSR_A4; + gdb_server_i.reg_tmp_num = RV_REG_A4; gdb_server_i.reg_tmp[0] = params3; rv_target_write_register(gdb_server_i.reg_tmp, gdb_server_i.reg_tmp_num);