Roadmap

Qucs Roadmap

This document describes the long term goals of the Qucs project. It should evolve with the user needs and provide focus to the development. This list provides a overview of current and future features. The list presented here is an extension of the original roadmap available in http://qucs.sourceforge.net/road.html.

This list should serve as base to track the status of each action point. Enhancements can be handled in two ways:

• For simpler enhancements an issue/bug ticket shall be created and referenced back here. The pertinent discussion and documentation should be done on the body of each ticket.
• For more complex enhancements a Qucs Enhancement Proposal should be created and reference back here.

The open action points can be further categorized concerning the difficulty or amount of work as (Easy, Medium, Hard) and priority (0-3, 0 is the highest). See the Port to Qt4 / Qt5 for an example.

Tickets will be tracked individually and assigned to milestones leading to stable releases.

Stage 1 - Simple GUI and simulator

• Support for multiple languages.
  • Means to translate the graphical user interface.
  • Means to translate the help and manuals.
• Support for standard types of simulations.
  • DC
  • Transient
  • Transient Noise Analysis
  • AC
  • AC Noise
  • S-Parameter
  • S-Parameter Noise
  • Harmonic Balance
• Create data representation, visualizations (diagrams).
• Implement an easy to use schematic editor.
• (H,0) Port to Qt4 / Qt5.
  • Port Qt3Support classes to Qt4.
  • Port schematic to Qt GraphicsView framework, [ QEP: QGraphicsView ]

Stage 2 - Implementation of powerful circuit analysis tools

• EM field simulator.
  • openEMS
  • FastHenry, FastCap
• Transient simulation using convolution for devices defined in the frequency domain.
• Digital simulation.
  • Icarus-Verilog
  • FreeHDL
  • GHDL
  • Verilator
• Co-simulation (analog + Verilog/VHDL)
  • simulator interfaces, VPI, PLI
• Improvements in the GUI regarding usability and design.
• Large signal S-parameter simulation (LSSP) based on harmonic balance.
• Symbolically defined devices.
• Verilog-AMS interface. [ QEP: Verilog-AMS interface ]
  • Static, compile time
  • Dynamic, interactive compile and load
  • Automatic compile and load modules based on annotated schematic/netlist
  • Command line interface
  • Use automatic differentiation (ADOL-C, Eigen Auto Diff) on Verilog-AMS interface.
• Use 3rd party libraries (algebra, solvers).
  • Eigen
  • KLU
• Code parallelization.
• Interface to high-level programming languages [ QEP: SWIG interface ]
  • Python
  • Octave
• Better SPICE compatibility.
  • SPICE 2g6, 3f5, PSpice, HSPICE, and XYCE formats
  • Enable the inclusion of .model cards into schematic components and netlist.
• Interface to other software tools
  • import/export schematic formats
  • import/export netlist formats
  • import/export data formats
• Efficient data storage
  • HDF5
• Support other simulation engines
  • ngspice
  • xyce
  • gnucap
• test/maintenance infrastructure
  • support for googletest (C++) framework
  • comprehensive unit test
  • system testing, qucs-test
    • test qucs schematic-to-netlist
    • test qucsator simulator
  • Continuous integration (Travis)
  • Static analysis (Clang Static Analyzer, Cppcheck)
  • Automated C++ code formatting (clang-format)
• Documentation
  • support for Doxygen
  • comprehensive C++ code documentation
  • tutorials, technical manuals in PDF (LaTex)
  • convert LaTex documentation to a format suitable for translation

Stage 3 - Support for more design and synthesis tools

• Attenuator design tool.
• Smith-Chart tool for noise and power matching
• Filter synthesis tool.
• Optimizer
  • ASCO.
• Transmission line calculator.
• Device model and subcircuit library manager.

Stage 4 - Implementation of industry standard device models.

• Implementation of BSIM series.
  • BSIM4
  • BSIM6
• Implementation of HICUM.
• Implementation of MEXTRAM.
• Implementation of VBIC.
• Implementation of EPFL-EKV.
• Implementation of HiSIM
• Implementation of IGBJT

Stage 5 - Design realization, production, verification.

• Layout editor for PCB and chip.
  • KiCad
  • KLayout
• Layout tools: DRC, ERC, LVS, ...
• Monte Carlo simulation (device mismatch and process mismatch) based on real technology data.
• Automated data acquisition from measurement equipment; ease the use of measurement setups.