Roadmap

Qucs Roadmap

Stage 1 - Simple GUI and simulator

• Support for multiple languages.
  • Means to translate the graphical user interface.
  • Means to translate the help and manuals.
• Support for standard types of simulations.
  • DC
  • Transient
  • AC
  • AC Noise
  • S-Parameter
  • S-Parameter Noise
  • Harmonic Balance
• Create data representation, visualizations (diagrams).
• Implement an easy to use schematic editor.
• Port to Qt4 / Qt5.
  • Port Qt3Support classes to Qt4.
  • Port the current graphics to Qt GraphicsView framework.

Stage 2 - Implementation of powerful circuit analysis tools

• EM field simulator.
  • openEMS
  • FastHenry, FastCap
• Transient simulation using convolution for devices defined in the frequency domain.
• Digital simulation.
  • Icarus-Verilog
  • FreeHDL
  • GHDL
• Improvements in the GUI regarding usability and design.
• Large signal S-parameter simulation (LSSP) based on harmonic balance.
• Symbolically defined devices.
• Verilog-AMS interface.
  • Static, compile time
  • Dynamic, interactive compile and load
  • Automatic compile and load modules based on annotated schematic/netlist
  • Command line interface
• Use 3rd party libraries (algebra, solvers).
  • Eigen
  • KLU
• Code parallelization.
• Use automatic differentiation (ADOL-C, Eigen Auto Diff) on Verilog-AMS interface.
• Co-simulation (analog + Verilog/VHDL)
  • simulator interfaces, VPI, PLI
• Interface to high-level programing languages (SWIG)
  • Python
  • Octave
• Better SPICE compatibility.
  • SPICE 2g6, 3f5, PSpice, HSPICE, and XYCE formats
  • Enable the inclusion of .model cards into schematic components and netlist.
• Interface to other software tools
  • import/export schematic formats
  • import/export netlist formats
  • import/export data formats
• Efficient data storage
  • HDF5
• Support other simulation engines
  • ngspice
  • xyce
  • gnucap
• testing infrastructure
  • support for googletest (C++) framework
  • comprehensive unit test
  • system testing, qucs-test
    • test qucs schematic-to-netlist
    • test qucsator simulator
• documentation

Stage 3 - Support for more design and synthesis tools

• Attenuator design tool.
• Smith-Chart tool for noise and power matching
• Filter synthesis tool.
• Optimizer
  • ASCO.
• Transmission line calculator.
• Device model and subcircuit library manager.

Stage 4 - Implementation of industry standard device models.

• Implementation of BSIM series.
  • BSIM4
  • BSIM6
• Implementation of HICUM.
• Implementation of MEXTRAM.
• Implementation of VBIC.
• Implementation of EPFL-EKV.

Stage 5 - Design realization, production, verification.

• Layout editor for PCB and chip.
  • KiCad
  • KLayout
• Layout tools: DRC, ERC, LVS, ...
• Monte Carlo simulation (device mismatch and process mismatch) based on real technology data.
• Automated data acquisition from measurement equipment; ease the use of measurement setups.