From 11344241b895b7f64c27144e8a271d950c00bcab Mon Sep 17 00:00:00 2001 From: Joshua DeWeese Date: Mon, 1 May 2023 16:17:25 -0400 Subject: [PATCH] cpu/stm32/periph/dac: optimize setting DAC The current implmentation right shifted the 16 bit value passed into `dac_set()` down to the 12 bits that the DAC is actually capable of. This patch drops the shift and instead writes the 16 bit value to the DAC's left aligned 12 bit wide data holding register. --- cpu/stm32/periph/dac.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/cpu/stm32/periph/dac.c b/cpu/stm32/periph/dac.c index 468bfa6c4aa5..c043269711cd 100644 --- a/cpu/stm32/periph/dac.c +++ b/cpu/stm32/periph/dac.c @@ -73,18 +73,15 @@ void dac_set(dac_t line, uint16_t value) { assert(line < DAC_NUMOF); - /* scale set value to 12-bit */ - value = (value >> 4); - -#ifdef DAC_DHR12R2_DACC2DHR +#ifdef DAC_DHR12L2_DACC2DHR if (dac_config[line].chan & 0x01) { - dev(line)->DHR12R2 = value; + dev(line)->DHR12L2 = value; } else { - dev(line)->DHR12R1 = value; + dev(line)->DHR12L1 = value; } #else - dev(line)->DHR12R1 = value; + dev(line)->DHR12L1 = value; #endif }