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add movbe
1 parent 35e8e17 commit 0040e92

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catnip/x64assembler.nim

+8
Original file line numberDiff line numberDiff line change
@@ -739,6 +739,14 @@ genAssembler cmov:
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(reg32, rm32, cond): (rex, 0x0F, 0x40 + ord(cond), modrm(rm, reg))
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(reg64, rm64, cond): (op64, 0x0F, 0x40 + ord(cond), modrm(rm, reg))
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genAssembler movbe:
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(reg16, rmMemOnly): (op16, rex, 0x0F, 0x38, 0xF0, modrm(rm, reg))
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(reg32, rmMemOnly): (rex, 0x0F, 0x38, 0xF0, modrm(rm, reg))
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(reg64, rmMemOnly): (op64, 0x0F, 0x38, 0xF0, modrm(rm, reg))
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(rmMemOnly, reg16): (op16, rex, 0x0F, 0x38, 0xF1, modrm(rm, reg))
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(rmMemOnly, reg32): (rex, 0x0F, 0x38, 0xF1, modrm(rm, reg))
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(rmMemOnly, reg64): (op64, 0x0F, 0x38, 0xF1, modrm(rm, reg))
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genAssembler cwd: (): (op16, 0x99)
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genAssembler cdq: (): (0x99)
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genAssembler cqo: (): (op64, 0x99)

tests/test1.nim

+13
Original file line numberDiff line numberDiff line change
@@ -342,6 +342,19 @@ proc main =
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s.jcc(condNotZero, funcStart)
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s.ret()
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s.movbe(regAx, memMemOnly(regRax))
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s.movbe(regAx, memMemOnly(regR15))
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s.movbe(regEax, memMemOnly(regRax))
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s.movbe(regEax, memMemOnly(regR15))
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s.movbe(regRax, memMemOnly(regRax))
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s.movbe(regRax, memMemOnly(regR15))
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s.movbe(memMemOnly(regRax), regAx)
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s.movbe(memMemOnly(regR15), regAx)
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s.movbe(memMemOnly(regRax), regEax)
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s.movbe(memMemOnly(regR15), regEax)
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s.movbe(memMemOnly(regRax), regRax)
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s.movbe(memMemOnly(regR15), regRax)
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let stream = newFileStream("assembled.bin", fmWrite)
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stream.writeData(addr data[0], s.offset)
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stream.close()

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