-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathgeneral.py
540 lines (429 loc) · 17.5 KB
/
general.py
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
from platform import machine
#--------------------------
# Colours
GREEN = "\x1b[38;5;47m"
BLUE = "\x1b[38;5;14m"
WHITE = "\x1b[38;5;255m"
GREY = "\x1b[38;5;246m"
RESET = "\x1b[0m"
NL = "\n\n"
#--------------------------
# Register list
reg_aarch64 = {"x0": 0, "x1": 1, "x2": 2, "x3": 3, "x4": 4, "x5": 5, "x6": 6, "x7": 7, "x8": 8,
"x9": 9, "x10": 10, "x11": 11, "x12": 12, "x13": 13, "x14": 14, "x15": 15, "x16": 16,
"x17": 17, "x18": 18, "x19": 19, "x20": 20, "x21": 21, "x22": 22, "x23": 23, "x24": 24,
"x25": 25, "x26": 26, "x27": 27, "x28": 28, "x29": 29, "x30": 30,
"b0": 31, "b1": 32, "b2": 33, "b3": 34, "b4": 35, "b5": 36, "b6": 37, "b7": 38, "b8": 39,
"b9": 40, "b10": 41, "b11": 42, "b12": 43, "b13": 44, "b14": 45, "b15": 46, "b16": 47,
"b17": 48, "b18": 49, "b19": 50, "b20": 51, "b21": 52, "b22": 53, "b23": 54, "b24": 55,
"b25": 56, "b26": 57, "b27": 58, "b28": 59, "b29": 60, "b30": 61, "b31": 62,
"h0": 63, "h1": 64, "h2": 65, "h3": 66, "h4": 67, "h5": 68, "h6": 69, "h7": 70, "h8": 71,
"h9": 72, "h10": 73, "h11": 74, "h12": 75, "h13": 76, "h14": 77, "h15": 78, "h16": 79,
"h17": 80, "h18": 81, "h19": 82, "h20": 83, "h21": 84, "h22": 85, "h23": 86, "h24": 87,
"h25": 88, "h26": 89, "h27": 90, "h28": 91, "h29": 92, "h30": 93, "h31": 94,
"s0": 95, "s1": 96, "s2": 97, "s3": 98, "s4": 99, "s5": 100, "s6": 101, "s7": 102, "s8": 103,
"s9": 104, "s10": 105, "s11": 106, "s12": 107, "s13": 108, "s14": 109, "s15": 110, "s16": 111,
"s17": 112, "s18": 113, "s19": 114, "s20": 115, "s21": 116, "s22": 117, "s23": 118, "s24": 119,
"s25": 120, "s26": 121, "s27": 122, "s28": 123, "s29": 124, "s30": 125, "s31": 126,
"d0": 127, "d1": 128, "d2": 129, "d3": 130, "d4": 131, "d5": 132, "d6": 133, "d7": 134, "d8": 135,
"d9": 136, "d10": 137, "d11": 138, "d12": 139, "d13": 140, "d14": 141, "d15": 142, "d16": 143,
"d17": 144, "d18": 145, "d19": 146, "d20": 147, "d21": 148, "d22": 149, "d23": 150, "d24": 151,
"d25": 152, "d26": 153, "d27": 154, "d28": 155, "d29": 156, "d30": 157, "d31": 158,
"q0": 159, "q1": 160, "q2": 161, "q3": 162, "q4": 163, "q5": 164, "q6": 165, "q7": 166, "q8": 167,
"q9": 168, "q10": 169, "q11": 170, "q12": 171, "q13": 172, "q14": 173, "q15": 174, "q16": 175,
"q17": 176, "q18": 177, "q19": 178, "q20": 179, "q21": 180, "q22": 181, "q23": 182, "q24": 183,
"q25": 184, "q26": 185, "q27": 186, "q28": 187, "q29": 188, "q30": 189, "q31": 190,
"v0": 191, "v1": 192, "v2": 193, "v3": 194, "v4": 195, "v5": 196, "v6": 197, "v7": 198, "v8": 199,
"v9": 200, "v10": 201, "v11": 202, "v12": 203, "v13": 204, "v14": 205, "v15": 206, "v16": 207,
"v17": 208, "v18": 209, "v19": 210, "v20": 211, "v21": 212, "v22": 213, "v23": 214, "v24": 215,
"v25": 216, "v26": 217, "v27": 218, "v28": 219, "v29": 220, "v30": 221, "v31": 222,
"w0": 223, "w1": 224, "w2": 225, "w3": 226, "w4": 227, "w5": 228, "w6": 229, "w7": 230, "w8": 231,
"w9": 232, "w10": 233, "w11": 234, "w12": 235, "w13": 236, "w14": 237, "w15": 238, "w16": 239,
"w17": 240, "w18": 241, "w19": 242, "w20": 243, "w21": 244, "w22": 245, "w23": 246, "w24": 247,
"w25": 248, "w26": 249, "w27": 250, "w28": 251, "w29": 252, "w30": 253,
"pc": 254, "sp": 255, "cpsr": 256, "fpsr": 257, "fpcr": 258, "lr": 259}
reg_armv8a = {"r0": 0, "r1": 1, "r2": 2, "r3": 3, "r4": 4, "r5": 5, "r6": 6, "r7": 7, "r8": 8,
"r9": 9, "r10": 10, "r11": 11, "r12": 12,
"s0": 13, "s1": 14, "s2": 15, "s3": 16, "s4": 17, "s5": 18, "s6": 19, "s7": 20, "s8": 21,
"s9": 22, "s10": 23, "s11": 24, "s12": 25, "s13": 26, "s14": 27, "s15": 28, "s16": 29,
"s17": 30, "s18": 31, "s19": 32, "s20": 33, "s21": 34, "s22": 35, "s23": 36, "s24": 37,
"s25": 38, "s26": 39, "s27": 40, "s28": 41, "s29": 42, "s30": 43, "s31": 44,
"d0": 45, "d1": 46, "d2": 47, "d3": 48, "d4": 49, "d5": 50, "d6": 51, "d7": 52, "d8": 53,
"d9": 54, "d10": 55, "d11": 56, "d12": 57, "d13": 58, "d14": 59, "d15": 60, "d16": 61,
"d17": 62, "d18": 63, "d19": 64, "d20": 65, "d21": 66, "d22": 67, "d23": 68, "d24": 69,
"d25": 70, "d26": 71, "d27": 72, "d28": 73, "d29": 74, "d30": 75, "d31": 76,
"q0": 77, "q1": 78, "q2": 79, "q3": 80, "q4": 81, "q5": 82, "q6": 83, "q7": 84, "q8": 85,
"q9": 86, "q10": 87, "q11": 88, "q12": 89, "q13": 90, "q14": 91, "q15": 92,
"lr": 93, "pc": 94, "sp": 95, "cpsr": 96, "fpscr": 97}
registers = reg_aarch64 if machine() == "aarch64" else reg_armv8a
#--------------------------
# class view of registers for formatting
class Register(object):
frame = None
def __init__(self, name):
self.name = name
self.val = None
self.fmt = 'd'
self.colour = WHITE
@classmethod
def Factory(self, name):
try:
if name[1:2].isdigit():
return reg_class[name[0:1]](name)
else:
return reg_special[name](name)
except:
raise BasicException("Invalid Register")
def __format__(self, format_spec):
return self.colour + format(str(self), format_spec)
def __str__(self):
return self.val.format_string(format=self.fmt)
def value(self):
val = Register.frame.read_register(self.name)
self.colour = BLUE if self.val != val else WHITE
self.val = val
return self.val
def is_vector(self):
return False
class XReg(Register):
pass
class HSDReg(Register):
def __init__(self, name):
super().__init__(name)
self.fmt = 'f'
def __str__(self):
if self.fmt == 'd':
self.fmt = 's'
if self.fmt in ['s', 'u', 'f']:
return self.val[self.fmt].format_string()
else:
return self.val['u'].format_string(format='z')
class BReg(Register):
def __str__(self):
return self.val['u'].format_string(format=self.fmt)
class QReg(Register):
def __format__(self, format_spec):
return self.colour + format(str(self), "<53")
def __str__(self):
return self.val['u'].format_string(format=self.fmt)
def is_vector(self):
return True
class VReg(Register):
def __format__(self, format_spec):
return self.colour + format(str(self), "<53")
def __str__(self):
return self.val['q']['u'][0].format_string(format=self.fmt)
def is_vector(self):
return True
class PCReg(Register):
def __init__(self, name):
super().__init__(name)
self.fmt = 'a'
class FPCRReg(Register):
def __str__(self):
flags = decode_fpcr(self.val)
hex = True if self.fmt == "z" or self.fmt == 'x' else False
return self.val.format_string(format='z') + " " + flags if hex else flags
class FPSRReg(Register):
def __str__(self):
flags = decode_fpsr(self.val)
hex = True if self.fmt == "z" or self.fmt == 'x' else False
return self.val.format_string(format='z') + " " + flags if hex else flags
class CPSRReg(Register):
def __str__(self):
flags, st = decode_cpsr(self.val, False)
hex = True if self.fmt == "z" or self.fmt == 'x' else False
return self.val.format_string(format='z') + " " + flags + st if hex else flags + st
# used to print floats in hex by casting the value to a pointer. We could use any pointer type really.
type_ptr_double = gdb.Value(0.0).type.pointer()
class SReg(Register):
def __str__(self):
hex = True if self.fmt == "z" or self.fmt == 'x' else False
return self.val.cast(type_ptr_double).format_string(format="z") if hex else self.val.format_string()
class DReg(Register):
def __init__(self, name):
super().__init__(name)
self.fmt = 'f'
def __str__(self):
return self.val['u64'].format_string(format=self.fmt)
# return self.val['u64'].format_string(format="z") if self.hex else self.val['f64'].format_string()
class Qav8Reg(Register):
def __format__(self, format_spec):
return self.colour + format(str(self), "<53")
def __str__(self):
return self.val["u64"][1].format_string(format="z") + " " + self.val["u64"][0].format_string(format="z")
def is_vector(self):
return True
class WReg(Register):
def value(self):
self.val = super().value() & 0xffffffff
return self.val
def __str__(self):
if self.fmt == 'd' and self.val > 0x7fffffff:
self.val = self.val | 0xffffffff00000000
return self.val.format_string(format=self.fmt)
class FPSCRReg(Register):
def __str__(self):
flags, st = decode_fpscr(self.val)
hex = True if self.fmt == "z" or self.fmt == 'x' else False
return " " + self.val.format_string(format='z') + " " + flags if hex else " " + flags + st
if machine() == "aarch64":
reg_class = {'x': XReg, 's': HSDReg, 'd': HSDReg, 'h': HSDReg, 'b': BReg, 'q': QReg, 'v': VReg, 'w': WReg}
reg_special = {'lr': PCReg, 'pc': PCReg, 'sp': PCReg, 'cpsr': CPSRReg, 'fpsr': FPSRReg, 'fpcr': FPCRReg}
else:
reg_class = {'r': XReg, 's': SReg, 'd': DReg, 'q': Qav8Reg}
reg_special = {'lr': PCReg, 'pc': PCReg, 'sp': PCReg, 'cpsr': CPSRReg, 'fpscr': FPSCRReg}
#--------------------------
# decode system registers
# cpsr flags
N_FLAG = 0x80000000 # Negative
Z_FLAG = 0x40000000 # Zero
C_FLAG = 0x20000000 # Carry
V_FLAG = 0x10000000 # Overflow
def decode_cpsr(reg, extra):
flags = ""
n = (reg & N_FLAG) == N_FLAG
z = (reg & Z_FLAG) == Z_FLAG
c = (reg & C_FLAG) == C_FLAG
v = (reg & V_FLAG) == V_FLAG
if n: flags +="N "
if z: flags +="Z "
if c: flags +="C "
if v: flags +="V"
if z: str = "EQ"
else: str = "NE"
# signed
if (not z) and n == v: str += " GT"
# if n == v: str += " GE"
if not n == v: str += " LT"
# if z or (not n == v): str += " LE"
if extra:
# unsigned
str += " -"
if c and not z: str += " HI" # greater than (Higher)
if c: str += " HS" # greater than, equal to
else: str += " LO" # less than (Lower)
if (not c) or z: str += " LS" # less than, equal to
#
str += " -"
if n: str += " MI"
else: str += " PL"
if v: str += " VS"
else: str += " VC"
return flags, str
# fpcr flags
RM_MASK = 0xc00000 # 23-22
RN_FLAG = 0x000000 # Round to nearest tie zero
RP_FLAG = 0x400000 # Round towards + infinity (ceil)
RM_FLAG = 0x800000 # Round towards - infinity (floor)
RZ_FLAG = 0xc00000 # Round towards zero (truncate)
DZE_FLAG = 0x200 # Divide by Zero Enabled
def decode_fpcr(reg):
mode = RM_MASK & reg
if mode == RN_FLAG:
str = "RN"
elif mode == RP_FLAG:
str = "RP"
elif mode == RM_FLAG:
str = "RM"
else:
str = "RZ"
if (reg & DZE_FLAG) == DZE_FLAG: str += " DZE"
return str
# fpsr flags
Q_FLAG = 0x08000000 # QC Saturation
D_FLAG = 0x00000002 # DZC Divide by zero
def decode_fpsr(reg):
str = ""
if (reg & Q_FLAG) == Q_FLAG: str += "QC "
if (reg & D_FLAG) == D_FLAG: str += "DZC"
return str
def decode_fpscr(reg):
flags = ""
n = (reg & N_FLAG) == N_FLAG
z = (reg & Z_FLAG) == Z_FLAG
c = (reg & C_FLAG) == C_FLAG
v = (reg & V_FLAG) == V_FLAG
if n: flags +="N "
if z: flags +="Z "
if c: flags +="C "
if v: flags +="V"
if z: str = "EQ"
else: str = "NE"
mode = RM_MASK & reg
if mode == RN_FLAG: str += " RN"
elif mode == RP_FLAG: str += "RP"
elif mode == RM_FLAG: str += "RM"
else: str += "RZ"
if (reg & DZE_FLAG) == DZE_FLAG: str += " DZE"
return flags, str
#--------------------------
# Register command and Register Window
class RegisterCmd(gdb.Command):
"""Add registers to the custom TUI Window register.
register OPT|/FMT register-list
/FMT: x: hex, z: zero pad hex, s: signed, u: unsigned, f: float, c: char
OPT: del register-list
clear - clear all registers from the window
save filename - save register-list to file (use so filename to read back)
Ranges can be specified with -"""
def __init__(self):
if machine() == "aarch64":
self.__doc__ += "\nregister x0 x10 - x15 s0 s4 - s6 d5 - d9 w0 w10 - w15\nSpecial registers: lr, pc, sp, cpsr, fpsr, fpcr"
else:
self.__doc__ += "\nregister r0 r10 - r15 s0 s4 - s6 d5 - d9\nSpecial registers: lr, pc, sp, cpsr, fpscr"
super(RegisterCmd, self).__init__("register", gdb.COMMAND_DATA)
self.win = None
def set_win(self, win):
self.win = win
def invoke(self, arguments, from_tty):
if self.win == None:
print("register: Tui Window not active.")
return
reg_list = []
prev = None
expand = False
delete = False
format = None
args = gdb.string_to_argv(arguments)
argc = len(args)
if argc == 0:
print("register register-list")
return
elif args[0][0:1] == '/':
if argc > 1:
f = args[0][1:2]
if f in ['x', 'z', 's', 'u', 'f', 'c']:
format = 'd' if f == 's' else f
else:
print(f'register /FMT: x, z, s, u, f or c expected: {f}')
return
del args[0]
else:
print(f'register /FMT register-list')
return
elif args[0] == "clear":
self.win.clear_registers()
return
elif args[0] == "del":
if argc > 1:
delete = True
del args[0]
else:
print("register del register-list")
return
elif args[0] == 'save':
if argc == 2:
self.win.save_registers(args[1])
return
else:
print("register save filename")
return
for reg in args:
if reg == "-":
expand = True
continue
elif not reg in registers:
print("register: invalid register %s" % reg)
return
if expand:
if prev == None:
print("register: no start to range")
return
start = registers[prev]
finish = registers[reg]
reg_list.extend([k for k, v in registers.items() if v > start and v <= finish])
expand = False
else:
prev = reg
reg_list.append(reg)
if delete:
self.win.del_registers(reg_list)
elif format is not None:
self.win.format_registers(reg_list, format)
else:
self.win.add_registers(reg_list)
regWinCmd = RegisterCmd()
def RegisterFactory(tui):
win = RegisterWindow(tui)
gdb.events.before_prompt.connect(win.create_register)
regWinCmd.set_win(win)
return win
class RegisterWindow(object):
regs_save = {}
def __init__(self, tui):
self.tui = tui
tui.title = "Registers"
self.regs = RegisterWindow.regs_save
self.start = 0
self.tui_list = []
def add_registers(self, list):
for name in list:
if not name in self.regs:
try:
self.regs[name] = Register.Factory(name)
except:
print(f'register: invalid register {name}.')
def del_registers(self, list):
for name in list:
try:
del self.regs[name]
except:
print(f'register del {name} not found')
def format_registers(self, args, format):
for name in args:
if not name in self.regs:
self.add_registers([name])
self.regs[name].fmt = format
def clear_registers(self):
self.regs.clear()
def save_registers(self, filename):
try:
with open(filename, "w") as f:
for name in self.regs:
f.write(f'reg {name}\n')
print(f'reg {name}')
except IOError:
print(f'reg: could not write to {filename}')
def close(self):
RegisterWindow.regs_save = self.regs
gdb.events.before_prompt.disconnect(self.create_register)
def render(self):
if not self.tui.is_valid():
return
self.tui.erase()
for l in self.tui_list[self.start:]:
self.tui.write(l)
def create_register(self):
self.tui_list = []
if not self.tui.is_valid():
return
try:
Register.frame = gdb.selected_frame()
except gdb.error:
self.start = 0
self.title = "No Frame"
self.tui_list.append("No frame currently selected" + NL)
self.render()
return
width = self.tui.width
line = ""
for name, reg in self.regs.items():
reg.value()
if width < 53 and reg.is_vector() or width < 29 and not reg.is_vector():
line += NL
self.tui_list.append(line)
line = ""
width = self.tui.width
line += f'{GREEN}{name:<5}{reg:<24}{RESET}'
width -= 53 if reg.is_vector() else 29
if line != "":
line += NL
self.tui_list.append(line)
self.render()
def vscroll(self, num):
if num > 0 and num + self.start < len(self.tui_list) or \
num < 0 and num + self.start >= 0:
self.start += num
self.render()
gdb.register_window_type("register", RegisterFactory)