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Increased the MaxBlock variable in the arb. prec. package. Build #85: Commit cd2457d pushed by cjhseger
February 25, 2025 09:44 4m 58s master
master
February 25, 2025 09:44 4m 58s
Fixed some g.c. bugs in the bv package. Build #84: Commit 883224e pushed by cjhseger
February 23, 2025 13:53 12m 5s master
master
February 23, 2025 13:53 12m 5s
Added support for the new IDELAY component in excitation_function. Build #83: Commit 6b60c47 pushed by cjhseger
February 3, 2025 16:21 16m 43s master
master
February 3, 2025 16:21 16m 43s
Added primitives to allow delay simulation using the XTBD-model. Build #82: Commit 4263a8a pushed by cjhseger
January 24, 2025 15:27 15m 58s master
master
January 24, 2025 15:27 15m 58s
Added an SMT example file. One trivial and one very difficult... Build #81: Commit a1f8de2 pushed by cjhseger
September 18, 2024 14:27 8m 6s master
master
September 18, 2024 14:27 8m 6s
Fixed the SMT interface for converting wexpr to SMT-LIB format. Build #80: Commit bf613ac pushed by cjhseger
September 18, 2024 14:20 7m 21s master
master
September 18, 2024 14:20 7m 21s
Added an interface to an SMT solver. Only tested against CVC5, but Build #79: Commit 42eb815 pushed by cjhseger
September 16, 2024 15:23 17m 34s master
master
September 16, 2024 15:23 17m 34s
Merge pull request #34 from tianrui-wei/tianrui-wei/fix-github-actions Build #78: Commit eb96ebb pushed by cjhseger
July 9, 2024 15:11 19m 23s master
master
July 9, 2024 15:11 19m 23s
chore(ci): fix ci Build #77: Pull request #34 synchronize by tianrui-wei
July 9, 2024 14:49 15m 40s tianrui-wei:tianrui-wei/fix-github-actions
tianrui-wei:tianrui-wei/fix-github-actions
July 9, 2024 14:49 15m 40s
chore(ci): fix ci Build #76: Pull request #34 synchronize by tianrui-wei
July 9, 2024 14:46 3m 50s tianrui-wei:tianrui-wei/fix-github-actions
tianrui-wei:tianrui-wei/fix-github-actions
July 9, 2024 14:46 3m 50s
chore(ci): fix ci Build #75: Pull request #34 opened by tianrui-wei
July 9, 2024 14:43 21s tianrui-wei:tianrui-wei/fix-github-actions
tianrui-wei:tianrui-wei/fix-github-actions
July 9, 2024 14:43 21s
Added the Bifrost language to the VossII/IDVII system. Build #74: Commit db91978 pushed by cjhseger
July 9, 2024 07:22 48s master
master
July 9, 2024 07:22 48s
Modified hfl so that leaf functions (W_UPDATE_FN and W_PHASE_DELAY) a… Build #73: Commit d987049 pushed by cjhseger
July 9, 2024 07:17 20s master
master
July 9, 2024 07:17 20s
Fixed a bug in the processing of inputs when a syntax error or type c… Build #72: Commit d7ec8ab pushed by cjhseger
July 5, 2024 13:01 20s master
master
July 5, 2024 13:01 20s
Fixed a silly bug that made the verification skip testing for the case Build #71: Commit b3d8826 pushed by cjhseger
April 26, 2024 15:25 1m 5s master
master
April 26, 2024 15:25 1m 5s
Moved the slist to vosslib since it is generally useful. Build #70: Commit 52eaf65 pushed by cjhseger
April 22, 2024 07:58 1m 57s master
master
April 22, 2024 07:58 1m 57s
Cleaned up the verification examples. Build #69: Commit 681a1c5 pushed by cjhseger
April 22, 2024 06:13 3m 1s master
master
April 22, 2024 06:13 3m 1s
An example using the same specification but for a different implement… Build #68: Commit 7524321 pushed by cjhseger
April 21, 2024 21:10 9m 58s master
master
April 21, 2024 21:10 9m 58s
Added an example of verifying a valid-ready buffer component. Build #67: Commit 0220a56 pushed by cjhseger
April 19, 2024 14:23 11m 49s master
master
April 19, 2024 14:23 11m 49s
Made bifrost clockgating logic more parameterized. Build #62: Commit d02e8b8 pushed by cjhseger
March 10, 2024 21:27 10m 22s master
master
March 10, 2024 21:27 10m 22s
Fixed the Verilog writer to handle nested slice operations. Build #61: Commit 1b21300 pushed by cjhseger
February 23, 2024 22:06 1m 22s master
master
February 23, 2024 22:06 1m 22s
Made the Yosys syntehsis IDV script callable directly from fl. Build #60: Commit 2d51b57 pushed by cjhseger
February 22, 2024 14:51 10m 57s master
master
February 22, 2024 14:51 10m 57s
Fixed a "bug" introduced in the previous checkin related to more modern Build #59: Commit df96fd7 pushed by cjhseger
February 13, 2024 16:11 10m 42s master
master
February 13, 2024 16:11 10m 42s
Fixed a serious bug in the iso-matching code that did not distinguish Build #58: Commit 210e95b pushed by cjhseger
January 31, 2024 21:20 1m 0s master
master
January 31, 2024 21:20 1m 0s
Some (minor) fixes in the Verilog writer to make sure it emits clean … Build #57: Commit de7c9ec pushed by cjhseger
January 31, 2024 08:54 1m 6s master
master
January 31, 2024 08:54 1m 6s