systeverilog && uvm

[Hard-studying-man]

I want to use this to do some systemverilog and uvm work. However,there exist errors woring when I creat a class it always show :"syntax error, unexpected IDENTIFIER". And when I need to creat a class that extens uvm class ,I get :"Error in class extension specification"
I do not how to set linters to avoid those errors.By the way,I use modelsim as my linters.

[qarlosalberto]

It's not possible for now
TerosTechnology/vscode-terosHDL#325