From 8032fa75a4eb31c761de260e1c0309343977f016 Mon Sep 17 00:00:00 2001
From: mole99 <leomoser99@gmail.com>
Date: Thu, 14 Dec 2023 16:44:09 +0100
Subject: [PATCH] Add LEF output for ROM

---
 compiler/modules/rom_bank.py |  4 +++-
 compiler/rom.py              | 10 ++++++++++
 rom_compiler.py              |  4 ++--
 3 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/compiler/modules/rom_bank.py b/compiler/modules/rom_bank.py
index 371a7f138..2cc3a7569 100644
--- a/compiler/modules/rom_bank.py
+++ b/compiler/modules/rom_bank.py
@@ -11,13 +11,14 @@
 from openram.base import vector
 from openram.base import design
 from openram.base import rom_verilog
+from openram.base import lef
 from openram import OPTS, print_time
 from openram.sram_factory import factory
 from openram.tech import spice
 from openram.tech import drc, layer, parameter
 
 
-class rom_bank(design,rom_verilog):
+class rom_bank(design, rom_verilog, lef):
 
     """
     Rom data bank with row and column decoder + control logic
@@ -27,6 +28,7 @@ class rom_bank(design,rom_verilog):
 
     def __init__(self, name, rom_config):
         super().__init__(name=name)
+        lef.__init__(self, ["m1", "m2", "m3", "m4"])
         self.rom_config = rom_config
         rom_config.set_local_config(self)
 
diff --git a/compiler/rom.py b/compiler/rom.py
index b997f0888..9911e8d47 100644
--- a/compiler/rom.py
+++ b/compiler/rom.py
@@ -59,6 +59,9 @@ def __init__(self, rom_config=None, name=None):
     def sp_write(self, name, lvs=False, trim=False):
         self.r.sp_write(name, lvs, trim)
 
+    def lef_write(self, name):
+        self.r.lef_write(name)
+
     def gds_write(self, name):
         self.r.gds_write(name)
 
@@ -106,6 +109,13 @@ def save(self):
                                         output_path=OPTS.output_path)
             print_time("GDS", datetime.datetime.now(), start_time)
 
+            # Create a LEF physical model
+            start_time = datetime.datetime.now()
+            lefname = OPTS.output_path + self.r.name + ".lef"
+            debug.print_raw("LEF: Writing to {0}".format(lefname))
+            self.lef_write(lefname)
+            print_time("LEF", datetime.datetime.now(), start_time)
+
         # Save the LVS file
         start_time = datetime.datetime.now()
         lvsname = OPTS.output_path + self.r.name + ".lvs.sp"
diff --git a/rom_compiler.py b/rom_compiler.py
index f09c1c0a6..65ac18474 100755
--- a/rom_compiler.py
+++ b/rom_compiler.py
@@ -51,7 +51,7 @@
 output_extensions = [ "sp", "v"]
 # Only output lef/gds if back-end
 if not OPTS.netlist_only:
-    output_extensions.extend(["gds"])
+    output_extensions.extend(["lef", "gds"])
 
 output_files = ["{0}{1}.{2}".format(OPTS.output_path,
                                     OPTS.output_name, x)
@@ -69,4 +69,4 @@
 
 # Delete temp files etc.
 openram.end_openram()
-openram.print_time("End", datetime.datetime.now(), start_time)
\ No newline at end of file
+openram.print_time("End", datetime.datetime.now(), start_time)