diff --git a/docker/Dockerfile b/docker/Dockerfile
index 6fb062c..73d9e50 100644
--- a/docker/Dockerfile
+++ b/docker/Dockerfile
@@ -73,7 +73,7 @@ RUN python -mpip install --upgrade pip && \
     rm requirements.txt
 
 # Install custom fork of pyverilator
-RUN pip install git+https://github.com/maltanar/pyverilator.git#egg=pyverilator
+RUN pip install git+https://github.com/maltanar/pyverilator.git@0c3eb9343500fc1352a02c020a736c8c2db47e8e
 
 # Install pytest-xdist (not in requirements, only for faster testing in Docker)
 RUN pip install pytest-xdist==2.0.0
diff --git a/src/finn/util/pyverilator.py b/src/finn/util/pyverilator.py
index b598a4a..49ab815 100644
--- a/src/finn/util/pyverilator.py
+++ b/src/finn/util/pyverilator.py
@@ -141,12 +141,20 @@ def rtlsim_multi_io(sim, io_dict, num_out_values, trace_file="", sname="_V_V_"):
     return total_cycle_count
 
 
-def pyverilate_stitched_ip(model, read_internal_signals=True):
+def pyverilate_stitched_ip(
+    model, read_internal_signals=True, disable_common_warnings=True
+):
     """Given a model with stitched IP, return a PyVerilator sim object.
-    If read_internal_signals is True, it will be possible to examine the
-    internal (not only port) signals of the Verilog module, but this may
-    slow down compilation and emulation.
     Trace depth is also controllable, see get_rtlsim_trace_depth()
+
+    :param read_internal_signals  If set, it will be possible to examine the
+        internal (not only port) signals of the Verilog module, but this may
+        slow down compilation and emulation.
+
+    :param disable_common_warnings If set, disable the set of warnings that
+        Vivado-HLS-generated Verilog typically triggers in Verilator
+        (which can be very verbose otherwise)
+
     """
     if PyVerilator is None:
         raise ImportError("Installation of PyVerilator is required.")
@@ -192,6 +200,19 @@ def file_to_basename(x):
                 wf.write("//Added from " + vfile + "\n\n")
                 wf.write(rf.read())
 
+    verilator_args = []
+    # disable common verilator warnings that should be harmless but commonly occur
+    # in large quantities for Vivado HLS-generated verilog code
+    if disable_common_warnings:
+        verilator_args += ["-Wno-STMTDLY"]
+        verilator_args += ["-Wno-PINMISSING"]
+        verilator_args += ["-Wno-IMPLICIT"]
+        verilator_args += ["-Wno-WIDTH"]
+        verilator_args += ["-Wno-COMBDLY"]
+    # force inlining of all submodules to ensure we can read internal signals properly
+    if read_internal_signals:
+        verilator_args += ["--inline-mult", "0"]
+
     sim = PyVerilator.build(
         top_module_file_name,
         verilog_path=[vivado_stitch_proj_dir],
@@ -200,6 +221,7 @@ def file_to_basename(x):
         top_module_name=top_module_name,
         auto_eval=False,
         read_internal_signals=read_internal_signals,
+        extra_args=verilator_args,
     )
     return sim