Set default value for a wire?

[ldoolitt]

I'd like to put a pulldown resistor on a wire in Verilog, to set a default value that will be used if it has no other drivers.
Things I've tried that don't work with yosys-0.40:

• wire x; pulldown(x);
• wire x; assign (weak1, weak0) x = 0;
• tri0 x;

Those latter two look like pretty standard Verilog to me.

[ldoolitt]

I also tried

• wire x; assign x = 1'bz;

That doesn't really do what I want, but I figured it will at least get rid of a bunch of 1'bx.
The syntax is accepted by the read_verilog step, at least, but died during a flatten -wb step.

[nakengelhardt]

Tristates are not supported in Yosys, except for limited support for using dedicated tristate I/O buffers on FPGA pins, for top level inout ports only.

If this is actually an internal wire (not an input of the current module) you can use wire x = 1'b0; or initial x = 1'b0; to initialize it, this will not conflict with other drivers in the module. If no other drivers are found in the module the initial value is kept. This may also work for wires that are module input ports if you are using flatten, but no guarantees and I think it does cause problems if opt is ever called on the non-flattened design.