Does Yosys Support Name Mapping Features Like Synopsys's guide_change_names or Cadence Conformal’s Register Mapping File?

[ApeachM]

Hello,

In Synopsys tools, the guide_change_names command within SVF files allows for tracking name changes during synthesis or ECO processes. Similarly, Cadence Conformal provides a Register Mapping File to handle name mapping between RTL designs and gate-level netlists, making it easier to maintain consistency during equivalence checking and ECO workflows.

Both of these name mapping methods are useful for verifying de#tegrity after optimizations or modifications by aligning instance and signal names across different design stages. I am wondering if Yosys supports any similar functionality or if there is a recommended way to achieve name mapping and tracking within the synthesis process.

Thank you !