memory_libmap: update indices on design modification #4892
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As reported in #4883, indices to the pass are reused after the module is modified, leading to dangling cell pointers in ModWalker etc. This has been the case since the inception of the pass but has only recently been discovered when 901935f exposed the issue as a segfault when a
PortBitis hashed. This issue is easily detected with valgrind but since there's limited use of valgrind in testing (vgtestMakefile target only runs simple tests due to the runtime, for example) we've missed it. Whether this has lead to incorrect mapping results is uncertain.This PR fixes the issue by rebuilding MapWorker but only when a memory actually gets emitted modifying the design. This rebuilds all the indices used in the and resolves anything detectable by valgrind at least on a clang debug build.
For testing with the segfault repro, see #4883 and run yosys with valgrind like
valgrind yosys -p "read_verilog ...