-
Notifications
You must be signed in to change notification settings - Fork 36
/
Copy pathboard.c
186 lines (168 loc) · 5.98 KB
/
board.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
/* SPDX-License-Identifier: GPL-2.0+ */
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <types.h>
#include <log.h>
#include <common.h>
#include <reg-ncat.h>
#include <sys-clk.h>
#include <mmu.h>
#include <sys-dram.h>
#include <sys-gpio.h>
#include <sys-i2c.h>
#include <sys-sdcard.h>
#include <sys-sid.h>
#include <sys-spi.h>
#include <sys-uart.h>
sunxi_serial_t uart_dbg = {
.base = SUNXI_UART3_BASE,
.id = 3,
.baud_rate = UART_BAUDRATE_115200,
.dlen = UART_DLEN_8,
.stop = UART_STOP_BIT_0,
.parity = UART_PARITY_NO,
.gpio_pin = {
.gpio_tx = {GPIO_PIN(GPIO_PORTB, 6), GPIO_PERIPH_MUX7},
.gpio_rx = {GPIO_PIN(GPIO_PORTB, 7), GPIO_PERIPH_MUX7},
},
.uart_clk = {
.gate_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.gate_reg_offset = 0 + 3,
.rst_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.rst_reg_offset = 16 + 3,
.parent_clk = 24000000,
},
};
sunxi_dma_t sunxi_dma = {
.dma_reg_base = SUNXI_DMA_BASE,
.bus_clk = {
.gate_reg_base = CCU_BASE + CCU_MBUS_MAT_CLK_GATING_REG,
.gate_reg_offset = DMA_DEFAULT_CLK_GATE_OFFSET,
},
.dma_clk = {
.rst_reg_base = CCU_BASE + CCU_DMA_BGR_REG,
.rst_reg_offset = DMA_DEFAULT_CLK_RST_OFFSET,
.gate_reg_base = CCU_BASE + CCU_DMA_BGR_REG,
.gate_reg_offset = DMA_DEFAULT_CLK_GATE_OFFSET,
},
};
sunxi_spi_t sunxi_spi0 = {
.base = 0x04025000,
.id = 0,
.clk_rate = 75 * 1000 * 1000,
.gpio = {
.gpio_cs = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX4},
.gpio_sck = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX4},
.gpio_mosi = {GPIO_PIN(GPIO_PORTC, 2), GPIO_PERIPH_MUX4},
.gpio_miso = {GPIO_PIN(GPIO_PORTC, 3), GPIO_PERIPH_MUX4},
.gpio_wp = {GPIO_PIN(GPIO_PORTC, 4), GPIO_PERIPH_MUX4},
.gpio_hold = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX4},
},
.spi_clk = {
.spi_clock_cfg_base = CCU_BASE + CCU_SPI0_CLK_REG,
.spi_clock_factor_n_offset = SPI_CLK_SEL_FACTOR_N_OFF,
.spi_clock_source = SPI_CLK_SEL_PERIPH_300M,
},
.parent_clk_reg = {
.rst_reg_base = CCU_BASE + CCU_SPI_BGR_REG,
.rst_reg_offset = SPI_DEFAULT_CLK_RST_OFFSET(0),
.gate_reg_base = CCU_BASE + CCU_SPI_BGR_REG,
.gate_reg_offset = SPI_DEFAULT_CLK_GATE_OFFSET(0),
.parent_clk = 300000000,
},
.dma_handle = &sunxi_dma,
};
sdhci_t sdhci0 = {
.name = "sdhci0",
.id = 0,
.reg = (sdhci_reg_t *) 0x04020000,
.voltage = MMC_VDD_27_36,
.width = MMC_BUS_WIDTH_4,
.clock = MMC_CLK_200M,
.removable = 0,
.isspi = FALSE,
.skew_auto_mode = TRUE,
.sdhci_pll = CCU_MMC_CTRL_PLL_PERIPH1X,
.gpio_clk = {GPIO_PIN(GPIO_PORTF, 2), GPIO_PERIPH_MUX2},
.gpio_cmd = {GPIO_PIN(GPIO_PORTF, 3), GPIO_PERIPH_MUX2},
.gpio_d0 = {GPIO_PIN(GPIO_PORTF, 1), GPIO_PERIPH_MUX2},
.gpio_d1 = {GPIO_PIN(GPIO_PORTF, 0), GPIO_PERIPH_MUX2},
.gpio_d2 = {GPIO_PIN(GPIO_PORTF, 5), GPIO_PERIPH_MUX2},
.gpio_d3 = {GPIO_PIN(GPIO_PORTF, 4), GPIO_PERIPH_MUX2},
};
sunxi_i2c_t i2c_pmu = {
.base = SUNXI_TWI0_BASE,
.id = SUNXI_I2C0,
.speed = SUNXI_I2C_SPEED_400K,
.gpio = {
.gpio_scl = {GPIO_PIN(GPIO_PORTL, 0), GPIO_PERIPH_MUX3},
.gpio_sda = {GPIO_PIN(GPIO_PORTL, 1), GPIO_PERIPH_MUX3},
},
.i2c_clk = {
.gate_reg_base = CCU_BASE + CCU_TWI_BGR_REG,
.gate_reg_offset = 0,
.rst_reg_base = CCU_BASE + CCU_TWI_BGR_REG,
.rst_reg_offset = 16,
.parent_clk = 24000000,
},
};
dram_para_t dram_para = {
.dram_clk = 792,
.dram_type = 3,
.dram_zq = 0x7b7bfb,
.dram_odt_en = 0x00,
.dram_para1 = 0x000010d2,
.dram_para2 = 0,
.dram_mr0 = 0x1c70,
.dram_mr1 = 0x42,
.dram_mr2 = 0x18,
.dram_mr3 = 0,
.dram_tpr0 = 0x004a2195,
.dram_tpr1 = 0x02423190,
.dram_tpr2 = 0x0008b061,
.dram_tpr3 = 0xb4787896,// unused
.dram_tpr4 = 0,
.dram_tpr5 = 0x48484848,
.dram_tpr6 = 0x00000048,
.dram_tpr7 = 0x1620121e,// unused
.dram_tpr8 = 0,
.dram_tpr9 = 0,// clock?
.dram_tpr10 = 0,
.dram_tpr11 = 0x00340000,
.dram_tpr12 = 0x00000046,
.dram_tpr13 = 0x34000100,
};
void clean_syterkit_data(void) {
/* Disable MMU, data cache, instruction cache, interrupts */
arm32_mmu_disable();
printk_info("disable mmu ok...\n");
arm32_dcache_disable();
printk_info("disable dcache ok...\n");
arm32_icache_disable();
printk_info("disable icache ok...\n");
arm32_interrupt_disable();
printk_info("free interrupt ok...\n");
}
void show_chip() {
uint32_t chip_sid[4];
chip_sid[0] = read32(SUNXI_SID_SRAM_BASE + 0x0);
chip_sid[1] = read32(SUNXI_SID_SRAM_BASE + 0x4);
chip_sid[2] = read32(SUNXI_SID_SRAM_BASE + 0x8);
chip_sid[3] = read32(SUNXI_SID_SRAM_BASE + 0xc);
printk_info("Model: Yuzuki Home Kit\n");
printk_info("Host Core: Arm Dual-Core Cortex-A7 R2P0\n");
printk_info("AMP Core: Xuantie C906 RISC-V RV64IMAFDCVX R1S0P2 Vlen=128\n");
printk_info("Chip SID = %08x%08x%08x%08x\n", chip_sid[0], chip_sid[1], chip_sid[2], chip_sid[3]);
uint32_t chip_markid_sid = chip_sid[0] & 0xffff;
switch (chip_markid_sid) {
case 0x7200:
printk_info("Chip type = T113M4020DC0");
break;
default:
printk_info("Chip type = UNKNOW");
break;
}
uint32_t version = read32(SUNXI_SYSCRL_BASE + 0x24) & 0x7;
printk(LOG_LEVEL_MUTE, " Chip Version = %x \n", version);
}