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spixpress.txt
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################################################################################
##
## Filename: spixpress.txt
## {{{
## Project: A Set of Wishbone Controlled SPI Flash Controllers
##
## Purpose: Describes the basic SPI flash peripheral for AutoFPGA.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2021, Gisselquist Technology, LLC
## {{{
## This file is part of the set of Wishbone controlled SPI flash controllers
## project
##
## The Wishbone SPI flash controller project is free software (firmware):
## you can redistribute it and/or modify it under the terms of the GNU Lesser
## General Public License as published by the Free Software Foundation, either
## version 3 of the License, or (at your option) any later version.
##
## The Wishbone SPI flash controller project is distributed in the hope
## that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
## warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU Lesser General Public License for more details.
##
## You should have received a copy of the GNU Lesser General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: LGPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/lgpl.html
##
##
################################################################################
##
## }}}
@PREFIX= flash
@DEVID=FLASH
@ACCESS= FLASH_ACCESS
@$LGFLASHSZ=24
@$NADDR=(1<<(@$LGFLASHSZ-2))
@$NBYTES=(1<<@$LGFLASHSZ)
@NBYTES.FORMAT=0x%08x
@ACCESS= FLASH_ACCESS
@SLAVE.TYPE=MEMORY
@SLAVE.BUS=wb
@TOP.PORTLIST=
// Top level SPI I/O ports
o_spi_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso
@TOP.IODECL=
// SPI flash
output wire o_spi_cs_n;
output wire o_spi_sck, o_spi_mosi;
input wire i_spi_miso;
@TOP.DEFNS=
wire spi_sck;
@TOP.MAIN=
// SPI flash
o_spi_cs_n, spi_sck, o_spi_mosi, i_spi_miso
@TOP.INSERT=
//
//
// Wires for setting up the SPI flash wishbone peripheral
//
//
oclkddr spi_ddr_sck(s_clk, {!spi_sck, 1'b1}, o_spi_sck);
@MAIN.PORTLIST=
// The SPI Flash
o_spi_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso
@MAIN.IODECL=
// The SPI flash
output wire o_spi_cs_n;
output wire o_spi_sck;
output wire o_spi_mosi;
input wire i_spi_miso;
@MAIN.INSERT=
spixpress @$(PREFIX)i(i_clk, i_reset,
(wb_cyc), (wb_stb)&&(@$(PREFIX)_sel),
(wb_stb)&&(flashcfg_sel), wb_we,
wb_addr[(@$LGFLASHSZ-3):0], wb_data,
@$(PREFIX)_stall, @$(PREFIX)_ack, @$(PREFIX)_data,
o_spi_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso);
@MAIN.ALT=
assign o_spi_cs_n = 1'b1;
assign o_spi_sck = 1'b0;
assign o_spi_mosi = 1'b1;
@MEM.NAME= flash
@MEM.ACCESS = rx
@REGS.N= 1
@REGDEFS.H.DEFNS=
#define @$(DEVID)BASE @$[0x%08x](REGBASE)
#define @$(DEVID)LEN @$NBYTES
#define @$(DEVID)LGLEN @$LGFLASHSZ
@REGS.0= 0 R_@$(DEVID) @$(DEVID)
@BDEF.OSDEF=_BOARD_HAS_@$(DEVID)
@BDEF.OSVAL=extern int _@$(PREFIX)[1];
@LD.PERM= rx
@LD.NAME= flash
@SIM.INCLUDE+=
#include "flashsim.h"
@SIM.DEFNS+=
#ifdef @$(ACCESS)
FLASHSIM *m_@$(MEM.NAME);
int m_@$(MEM.NAME)_last_sck;
#endif // @$(ACCESS)
@SIM.INIT+=
#ifdef @$(ACCESS)
m_@$(MEM.NAME) = new FLASHSIM(FLASHLGLEN);
m_@$(MEM.NAME)_last_sck = 0;
#endif // @$(ACCESS)
@SIM.TICK +=
#ifdef @$(ACCESS)
if (m_@$(MEM.NAME)_last_sck) {
(*m_@$(MEM.NAME))(m_core->o_spi_cs_n, 0,
m_core->o_spi_mosi);
} m_core->i_spi_miso =(((*m_@$(MEM.NAME))(m_core->o_spi_cs_n, 1,
m_core->o_spi_mosi))&2)?1:0;
m_@$(MEM.NAME)_last_sck = m_core->o_spi_sck;
#endif
@SIM.LOAD +=
#ifdef @$(ACCESS)
m_@$(MEM.NAME)->load(start, &buf[offset], wlen);
#endif // @$(ACCESS)
##
##
##
##
##
@RTL.MAKE.GROUP= FLASH
@RTL.MAKE.FILES= spixpress.v oclkddr.v
##
## Now the control interface
##
##
@PREFIX=flashcfg
@NADDR= 1
@ACCESS=FLASHCFG_ACCESS
@DEPENDS= FLASH_ACCESS
@DEVID=FLASHCFG
# This cannot be a DOUBLE peripheral type, since our response may take more
# than two clock cycles.
@SLAVE.TYPE=OTHER
@SLAVE.BUS=wb
@MAIN.INSERT=
// The Flash control interface result comes back together with the
// flash interface itself. Hence, we always return zero here.
assign flashcfg_ack = 1'b0;
assign flashcfg_stall = 1'b0;
assign flashcfg_data = 0;
@REGS.NOTE= // FLASH erase/program configuration registers
@REGS.N=1
@REGS.0= 0 R_FLASHCFG FLASHCFG QSPIC
@REGDEFS.H.INSERT=
// Flash control constants
#define SZPAGEB 256
#define PGLENB 256
#define SZPAGEW 64
#define PGLENW 64
#define NPAGES 256
#define SECTORSZB (NPAGES * SZPAGEB) // In bytes, not words!!
#define SECTORSZW (NPAGES * SZPAGEW) // In words
#define NSECTORS 64
#define SECTOROF(A) ((A) & (-1<<16))
#define SUBSECTOROF(A) ((A) & (-1<<12))
#define PAGEOF(A) ((A) & (-1<<8))
@BDEF.IONAME= io_flctl
@BDEF.OSDEF= _BOARD_HAS_@$(DEVID)
@BDEF.IOTYPE=unsigned
@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) * const @$(BDEF.IONAME) = ((@$BDEF.IOTYPE *)(@$[0x%08x](REGBASE)));
@RTL.MAKE.GROUP= FLASH
@RTL.MAKE.FILES=spixpress.v