This analyzer is useful for PDM streams. It counts the number of 1s present on the data line for a given clock's rising edges. In PDM terms, that means it only does the first channel. It doesn't handle stereo currently.
It does its best to start with the clock signal. However, it may be shifted against the samples you receive in your code. Changing the bits per sample configuration sample to 1 can make it easy to read individual bits instead of the ones count for a set of bits.
Use the Visual Studio project to compile.
python build_analyzer.pySet the search path for plugins to the release directory within your clone of
this repo.
To find the setting:
- Open the Options drop down in the top right.
- Select Preferences
- Select the Developer tab.
- The analyzer path is first in the pane.
Now, reload Logic and select PDM from the Analyzer drop down.
Please see the Sample Analyzer for detailed build instructions.