diff --git a/amaranth/back/rtlil.py b/amaranth/back/rtlil.py
index 196640713..8179c3cca 100644
--- a/amaranth/back/rtlil.py
+++ b/amaranth/back/rtlil.py
@@ -888,8 +888,13 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
                 if len(value) > 0 or sub_type == "$mem_v2":
                     sub_ports[port] = rhs_compiler(value)
 
+            if isinstance(subfragment, ir.Instance):
+                src = _src(subfragment.src_loc)
+            else:
+                src = ""
+
             module.cell(sub_type, name=sub_name, ports=sub_ports, params=sub_params,
-                        attrs=subfragment.attrs)
+                        attrs=subfragment.attrs, src=src)
 
         # If we emit all of our combinatorial logic into a single RTLIL process, Verilog
         # simulators will break horribly, because Yosys write_verilog transforms RTLIL processes
diff --git a/amaranth/hdl/ir.py b/amaranth/hdl/ir.py
index 16aab52dd..0b7139b7d 100644
--- a/amaranth/hdl/ir.py
+++ b/amaranth/hdl/ir.py
@@ -3,6 +3,7 @@
 from functools import reduce
 import warnings
 
+from .. import tracer
 from .._utils import *
 from .._unused import *
 from .ast import *
@@ -617,12 +618,13 @@ def _assign_names_to_fragments(self, hierarchy=("top",), *, _names=None):
 
 
 class Instance(Fragment):
-    def __init__(self, type, *args, **kwargs):
+    def __init__(self, type, *args, src_loc=None, src_loc_at=0, **kwargs):
         super().__init__()
 
         self.type        = type
         self.parameters  = OrderedDict()
         self.named_ports = OrderedDict()
+        self.src_loc     = src_loc or tracer.get_src_loc(src_loc_at)
 
         for (kind, name, value) in args:
             if kind == "a":
diff --git a/amaranth/hdl/mem.py b/amaranth/hdl/mem.py
index da59cdb55..94ffe8fe6 100644
--- a/amaranth/hdl/mem.py
+++ b/amaranth/hdl/mem.py
@@ -166,6 +166,7 @@ def elaborate(self, platform):
             i_WR_EN=Cat(Cat(en_bit.replicate(port.granularity) for en_bit in port.en) for port in self._write_ports),
             i_WR_ADDR=Cat(port.addr for port in self._write_ports),
             i_WR_DATA=Cat(port.data for port in self._write_ports),
+            src_loc=self.src_loc,
         )
         for port in self._read_ports:
             port._MustUse__used = True
diff --git a/amaranth/hdl/xfrm.py b/amaranth/hdl/xfrm.py
index 66e6c20ae..c56dbe0ac 100644
--- a/amaranth/hdl/xfrm.py
+++ b/amaranth/hdl/xfrm.py
@@ -263,7 +263,7 @@ def map_drivers(self, fragment, new_fragment):
 
     def on_fragment(self, fragment):
         if isinstance(fragment, Instance):
-            new_fragment = Instance(fragment.type)
+            new_fragment = Instance(fragment.type, src_loc=fragment.src_loc)
             new_fragment.parameters = OrderedDict(fragment.parameters)
             self.map_named_ports(fragment, new_fragment)
         else: