docs: axi_dmac: Update documentation

Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>

Author: podgori

docs/library/axi_dmac/index.rst

@@ -670,6 +670,25 @@ flag signal. For the AXI-Streaming interface the synchronization flag is carried
 in ``s_axis_user[0]``. In both cases the synchronization flag is qualified by
 the same control signal as the data.
 
+Cache Coherency
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To enable Cache Coherency between the DMA and the CPU, the ``CACHE_COHERENT``
+HDL synthesis configuration parameter must be set.
+
+Two additional parameters are used to configure the Cache Coherent transactions:
+
+-  ``AXI_AXCACHE`` sets the ARCACHE/AWCACHE AXI cache support signals;
+-  ``AXI_AXPROT`` sets the ARPROT/AWPROT AXI access permission signals.
+
+They are initially set to the following default values through ``CACHE_COHERENT``:
+
+-  ``AXI_AXCACHE`` = ``CACHE_COHERENT`` ? ``4'b1111`` : ``4'b0011``
+-  ``AXI_AXPROT`` = ``CACHE_COHERENT`` ? ``3'b010``  : ``3'b000``
+
+If Cache Coherency is enabled, the ``AXI_AXCACHE`` and ``AXI_AXPROT`` values can
+be changed to support systems with different caching policies.
+
 Diagnostics interface
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 

docs/regmap/adi_regmap_dmac.txt

@@ -9,7 +9,7 @@ ENDTITLE
 REG
 0x000
 VERSION
-Version of the peripheral. Follows semantic versioning. Current version 4.05.61.
+Version of the peripheral. Follows semantic versioning. Current version 4.05.62.
 ENDREG
 
 FIELD
@@ -25,7 +25,7 @@ RO
 ENDFIELD
 
 FIELD
-[7:0] 0x61
+[7:0] 0x62
 VERSION_PATCH
 RO
 ENDFIELD
@@ -80,7 +80,7 @@ ENDFIELD
 
 REG
 0x004
-INTERFACE_DESCRIPTION
+INTERFACE_DESCRIPTION_1
 ENDREG
 
 FIELD
@@ -123,6 +123,35 @@ ENDFIELD
 ############################################################################################
 ############################################################################################
 
+REG
+0x005
+INTERFACE_DESCRIPTION_2
+ENDREG
+
+FIELD
+[0] ''CACHE_COHERENT''
+CACHE_COHERENT
+R
+Value of ''CACHE_COHERENT'' parameter.(0 - Disabled, 1 -  Enabled )
+ENDFIELD
+
+FIELD
+[7:4] ''AXI_AXCACHE''
+AXI_AXCACHE
+R
+Value of ''AXI_AXCACHE'' parameter.
+ENDFIELD
+
+FIELD
+[10:8] ''AXI_AXPROT''
+AXI_AXPROT
+R
+Value of ''AXI_AXPROT'' parameter.
+ENDFIELD
+
+############################################################################################
+############################################################################################
+
 REG
 0x020
 IRQ_MASK