From 82b5d5ed4752da488344c85371e16792fab67df7 Mon Sep 17 00:00:00 2001 From: Elena-Hadarau_adi Date: Thu, 27 Mar 2025 14:25:50 +0200 Subject: [PATCH 1/3] project: Add xcvr_wizard project The project is designed to automatically generate xcvr parameters for specific configurations. Signed-off-by: Elena-Hadarau_adi --- projects/xcvr_wizard/Makefile | 7 +++++++ .../xcvr_wizard/common/xcvr_wizard_bd.tcl | 4 ++++ projects/xcvr_wizard/kc705/Makefile | 9 +++++++++ projects/xcvr_wizard/kc705/system_bd.tcl | 11 +++++++++++ projects/xcvr_wizard/kc705/system_project.tcl | 19 +++++++++++++++++++ projects/xcvr_wizard/kcu105/Makefile | 9 +++++++++ projects/xcvr_wizard/kcu105/system_bd.tcl | 11 +++++++++++ .../xcvr_wizard/kcu105/system_project.tcl | 19 +++++++++++++++++++ projects/xcvr_wizard/vcu118/Makefile | 9 +++++++++ projects/xcvr_wizard/vcu118/system_bd.tcl | 11 +++++++++++ .../xcvr_wizard/vcu118/system_project.tcl | 19 +++++++++++++++++++ projects/xcvr_wizard/zc706/Makefile | 9 +++++++++ projects/xcvr_wizard/zc706/system_bd.tcl | 11 +++++++++++ projects/xcvr_wizard/zc706/system_project.tcl | 19 +++++++++++++++++++ projects/xcvr_wizard/zcu102/Makefile | 9 +++++++++ projects/xcvr_wizard/zcu102/system_bd.tcl | 11 +++++++++++ .../xcvr_wizard/zcu102/system_project.tcl | 19 +++++++++++++++++++ 17 files changed, 206 insertions(+) create mode 100644 projects/xcvr_wizard/Makefile create mode 100644 projects/xcvr_wizard/common/xcvr_wizard_bd.tcl create mode 100644 projects/xcvr_wizard/kc705/Makefile create mode 100644 projects/xcvr_wizard/kc705/system_bd.tcl create mode 100644 projects/xcvr_wizard/kc705/system_project.tcl create mode 100644 projects/xcvr_wizard/kcu105/Makefile create mode 100644 projects/xcvr_wizard/kcu105/system_bd.tcl create mode 100644 projects/xcvr_wizard/kcu105/system_project.tcl create mode 100644 projects/xcvr_wizard/vcu118/Makefile create mode 100644 projects/xcvr_wizard/vcu118/system_bd.tcl create mode 100644 projects/xcvr_wizard/vcu118/system_project.tcl create mode 100644 projects/xcvr_wizard/zc706/Makefile create mode 100644 projects/xcvr_wizard/zc706/system_bd.tcl create mode 100644 projects/xcvr_wizard/zc706/system_project.tcl create mode 100644 projects/xcvr_wizard/zcu102/Makefile create mode 100644 projects/xcvr_wizard/zcu102/system_bd.tcl create mode 100644 projects/xcvr_wizard/zcu102/system_project.tcl diff --git a/projects/xcvr_wizard/Makefile b/projects/xcvr_wizard/Makefile new file mode 100644 index 00000000000..1402069e104 --- /dev/null +++ b/projects/xcvr_wizard/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/xcvr_wizard/common/xcvr_wizard_bd.tcl b/projects/xcvr_wizard/common/xcvr_wizard_bd.tcl new file mode 100644 index 00000000000..50b86c3eb1b --- /dev/null +++ b/projects/xcvr_wizard/common/xcvr_wizard_bd.tcl @@ -0,0 +1,4 @@ +############################################################################### +## Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### diff --git a/projects/xcvr_wizard/kc705/Makefile b/projects/xcvr_wizard/kc705/Makefile new file mode 100644 index 00000000000..075c80dff7d --- /dev/null +++ b/projects/xcvr_wizard/kc705/Makefile @@ -0,0 +1,9 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := xcvr_wizard_kc705 + +include ../../scripts/project-xilinx.mk diff --git a/projects/xcvr_wizard/kc705/system_bd.tcl b/projects/xcvr_wizard/kc705/system_bd.tcl new file mode 100644 index 00000000000..8fac0855c90 --- /dev/null +++ b/projects/xcvr_wizard/kc705/system_bd.tcl @@ -0,0 +1,11 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set LANE_RATE $ad_project_params(LANE_RATE) ; # [gbps] +set PLL_TYPE $ad_project_params(PLL_TYPE) ; # [CPLL/QPLL] +set REF_CLK $ad_project_params(REF_CLK) ; # [MHz] + +source $ad_hdl_dir/projects/scripts/gtwizard_generator.tcl +get_diff_params $LANE_RATE $PLL_TYPE $REF_CLK diff --git a/projects/xcvr_wizard/kc705/system_project.tcl b/projects/xcvr_wizard/kc705/system_project.tcl new file mode 100644 index 00000000000..0dac71fb63d --- /dev/null +++ b/projects/xcvr_wizard/kc705/system_project.tcl @@ -0,0 +1,19 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL] + +adi_project xcvr_wizard_kc705 0 [list \ + LANE_RATE [get_env_param LANE_RATE 10 ] \ + REF_CLK [get_env_param REF_CLK 500 ] \ + PLL_TYPE [get_env_param PLL_TYPE QPLL ] \ +] diff --git a/projects/xcvr_wizard/kcu105/Makefile b/projects/xcvr_wizard/kcu105/Makefile new file mode 100644 index 00000000000..aed847db21d --- /dev/null +++ b/projects/xcvr_wizard/kcu105/Makefile @@ -0,0 +1,9 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := xcvr_wizard_kcu105 + +include ../../scripts/project-xilinx.mk diff --git a/projects/xcvr_wizard/kcu105/system_bd.tcl b/projects/xcvr_wizard/kcu105/system_bd.tcl new file mode 100644 index 00000000000..ae6c8b72824 --- /dev/null +++ b/projects/xcvr_wizard/kcu105/system_bd.tcl @@ -0,0 +1,11 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set LANE_RATE $ad_project_params(LANE_RATE) ; # [gbps] +set PLL_TYPE $ad_project_params(PLL_TYPE) ; # [CPLL/QPLL0/QPLL1] +set REF_CLK $ad_project_params(REF_CLK) ; # [MHz] + +source $ad_hdl_dir/projects/scripts/gtwizard_generator.tcl +get_diff_params $LANE_RATE $PLL_TYPE $REF_CLK diff --git a/projects/xcvr_wizard/kcu105/system_project.tcl b/projects/xcvr_wizard/kcu105/system_project.tcl new file mode 100644 index 00000000000..558487f99ec --- /dev/null +++ b/projects/xcvr_wizard/kcu105/system_project.tcl @@ -0,0 +1,19 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL0/QPLL1] + +adi_project xcvr_wizard_kcu105 0 [list \ + LANE_RATE [get_env_param LANE_RATE 10 ] \ + REF_CLK [get_env_param REF_CLK 500 ] \ + PLL_TYPE [get_env_param PLL_TYPE QPLL0 ] \ +] diff --git a/projects/xcvr_wizard/vcu118/Makefile b/projects/xcvr_wizard/vcu118/Makefile new file mode 100644 index 00000000000..156ccd2c696 --- /dev/null +++ b/projects/xcvr_wizard/vcu118/Makefile @@ -0,0 +1,9 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := xcvr_wizard_vcu118 + +include ../../scripts/project-xilinx.mk diff --git a/projects/xcvr_wizard/vcu118/system_bd.tcl b/projects/xcvr_wizard/vcu118/system_bd.tcl new file mode 100644 index 00000000000..ae6c8b72824 --- /dev/null +++ b/projects/xcvr_wizard/vcu118/system_bd.tcl @@ -0,0 +1,11 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set LANE_RATE $ad_project_params(LANE_RATE) ; # [gbps] +set PLL_TYPE $ad_project_params(PLL_TYPE) ; # [CPLL/QPLL0/QPLL1] +set REF_CLK $ad_project_params(REF_CLK) ; # [MHz] + +source $ad_hdl_dir/projects/scripts/gtwizard_generator.tcl +get_diff_params $LANE_RATE $PLL_TYPE $REF_CLK diff --git a/projects/xcvr_wizard/vcu118/system_project.tcl b/projects/xcvr_wizard/vcu118/system_project.tcl new file mode 100644 index 00000000000..d862cad3b10 --- /dev/null +++ b/projects/xcvr_wizard/vcu118/system_project.tcl @@ -0,0 +1,19 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL0/QPLL1] + +adi_project xcvr_wizard_vcu118 0 [list \ + LANE_RATE [get_env_param LANE_RATE 10 ] \ + REF_CLK [get_env_param REF_CLK 500 ] \ + PLL_TYPE [get_env_param PLL_TYPE QPLL0 ] \ +] diff --git a/projects/xcvr_wizard/zc706/Makefile b/projects/xcvr_wizard/zc706/Makefile new file mode 100644 index 00000000000..bd48ff10adf --- /dev/null +++ b/projects/xcvr_wizard/zc706/Makefile @@ -0,0 +1,9 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := xcvr_wizard_zc706 + +include ../../scripts/project-xilinx.mk diff --git a/projects/xcvr_wizard/zc706/system_bd.tcl b/projects/xcvr_wizard/zc706/system_bd.tcl new file mode 100644 index 00000000000..8fac0855c90 --- /dev/null +++ b/projects/xcvr_wizard/zc706/system_bd.tcl @@ -0,0 +1,11 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set LANE_RATE $ad_project_params(LANE_RATE) ; # [gbps] +set PLL_TYPE $ad_project_params(PLL_TYPE) ; # [CPLL/QPLL] +set REF_CLK $ad_project_params(REF_CLK) ; # [MHz] + +source $ad_hdl_dir/projects/scripts/gtwizard_generator.tcl +get_diff_params $LANE_RATE $PLL_TYPE $REF_CLK diff --git a/projects/xcvr_wizard/zc706/system_project.tcl b/projects/xcvr_wizard/zc706/system_project.tcl new file mode 100644 index 00000000000..bb191e6a7e6 --- /dev/null +++ b/projects/xcvr_wizard/zc706/system_project.tcl @@ -0,0 +1,19 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL] + +adi_project xcvr_wizard_zc706 0 [list \ + LANE_RATE [get_env_param LANE_RATE 10 ] \ + REF_CLK [get_env_param REF_CLK 500 ] \ + PLL_TYPE [get_env_param PLL_TYPE QPLL ] \ +] diff --git a/projects/xcvr_wizard/zcu102/Makefile b/projects/xcvr_wizard/zcu102/Makefile new file mode 100644 index 00000000000..c71b35c4d9c --- /dev/null +++ b/projects/xcvr_wizard/zcu102/Makefile @@ -0,0 +1,9 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := xcvr_wizard_zcu102 + +include ../../scripts/project-xilinx.mk diff --git a/projects/xcvr_wizard/zcu102/system_bd.tcl b/projects/xcvr_wizard/zcu102/system_bd.tcl new file mode 100644 index 00000000000..ae6c8b72824 --- /dev/null +++ b/projects/xcvr_wizard/zcu102/system_bd.tcl @@ -0,0 +1,11 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set LANE_RATE $ad_project_params(LANE_RATE) ; # [gbps] +set PLL_TYPE $ad_project_params(PLL_TYPE) ; # [CPLL/QPLL0/QPLL1] +set REF_CLK $ad_project_params(REF_CLK) ; # [MHz] + +source $ad_hdl_dir/projects/scripts/gtwizard_generator.tcl +get_diff_params $LANE_RATE $PLL_TYPE $REF_CLK diff --git a/projects/xcvr_wizard/zcu102/system_project.tcl b/projects/xcvr_wizard/zcu102/system_project.tcl new file mode 100644 index 00000000000..6d9510b963d --- /dev/null +++ b/projects/xcvr_wizard/zcu102/system_project.tcl @@ -0,0 +1,19 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL0/QPLL1] + +adi_project xcvr_wizard_zcu102 0 [list \ + LANE_RATE [get_env_param LANE_RATE 10 ] \ + REF_CLK [get_env_param REF_CLK 500 ] \ + PLL_TYPE [get_env_param PLL_TYPE QPLL0 ] \ +] From b7a99718c2f162086285ba06136408a9ade76e93 Mon Sep 17 00:00:00 2001 From: Elena-Hadarau_adi Date: Thu, 27 Mar 2025 14:39:28 +0200 Subject: [PATCH 2/3] scripts: Add xcvr automation scripts These scripts are used to import the generated parameters from the xcvr_wizard project to the project in use. Signed-off-by: Elena-Hadarau_adi --- library/xilinx/scripts/xcvr_automation.tcl | 185 +++++++++++++++++++++ projects/scripts/adi_project_xilinx.tcl | 83 +++++++++ projects/scripts/gtwizard_generator.tcl | 70 ++++---- 3 files changed, 307 insertions(+), 31 deletions(-) create mode 100644 library/xilinx/scripts/xcvr_automation.tcl diff --git a/library/xilinx/scripts/xcvr_automation.tcl b/library/xilinx/scripts/xcvr_automation.tcl new file mode 100644 index 00000000000..94754f6036f --- /dev/null +++ b/library/xilinx/scripts/xcvr_automation.tcl @@ -0,0 +1,185 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +proc adi_xcvr_parameters {file_paths parameters} { + + set default_parameters { + "RX_NUM_OF_LANES" "8" + "TX_NUM_OF_LANES" "8" + "RX_LANE_RATE" "12.5" + "TX_LANE_RATE" "12.5" + "LINK_MODE" "1" + "RX_LANE_INVERT" "0" + "TX_LANE_INVERT" "0" + "QPLL_REFCLK_DIV" "1" + "QPLL_FBDIV_RATIO" "1" + "POR_CFG" "16'b0000000000000110" + "PPF0_CFG" "16'b0000011000000000" + "PPF1_CFG" "16'b0000011000000000" + "QPLL_CFG" "27'h0680181" + "QPLL_FBDIV" "10'b0000110000" + "QPLL_CFG0" "16'b0011001100011100" + "QPLL_CFG1" "16'b1101000000111000" + "QPLL_CFG1_G3" "16'b1101000000111000" + "QPLL_CFG2" "16'b0000111111000000" + "QPLL_CFG2_G3" "16'b0000111111000000" + "QPLL_CFG3" "16'b0000000100100000" + "QPLL_CFG4" "16'b0000000000000011" + "QPLL_CP_G3" "10'b0000011111" + "QPLL_LPF" "10'b0100110111" + "QPLL_CP" "10'b0001111111" + "CPLL_FBDIV" "2" + "CPLL_FBDIV_4_5" "5" + "CPLL_CFG0" "16'b0000000111111010" + "CPLL_CFG1" "16'b0000000000100011" + "CPLL_CFG2" "16'b0000000000000010" + "CPLL_CFG3" "16'b0000000000000000" + "CH_HSPMUX" "16'b0010010000100100" + "PREIQ_FREQ_BST" "0" + "RXPI_CFG0" "16'b0000000000000010" + "RXPI_CFG1" "16'b0000000000010101" + "RTX_BUF_CML_CTRL" "3'b011" + "TX_OUT_DIV" "1" + "TX_CLK25_DIV" "20" + "TX_PI_BIASSET" "1" + "TXPI_CFG" "16'b0000000001010100" + "A_TXDIFFCTRL" "5'b10110" + "RX_OUT_DIV" "1" + "RX_CLK25_DIV" "20" + "RX_DFE_LPM_CFG" "16'h0104" + "RX_PMA_CFG" "32'h001e7080" + "RX_CDR_CFG" "72'h0b000023ff10400020" + "RXCDR_CFG0" "16'b0000000000000010" + "RXCDR_CFG2" "16'b0000001001101001" + "RXCDR_CFG2_GEN2" "10'b1001100101" + "RXCDR_CFG2_GEN4" "16'b0000000010110100" + "RXCDR_CFG3" "16'b0000000000010010" + "RXCDR_CFG3_GEN2" "6'b011010" + "RXCDR_CFG3_GEN3" "16'b0000000000010010" + "RXCDR_CFG3_GEN4" "16'b0000000000100100" + "RXDFE_KH_CFG2" "16'h0200" + "RXDFE_KH_CFG3" "16'h4101" + "RX_WIDEMODE_CDR" "2'b00" + "RX_XMODE_SEL" "1'b1" + "TXDRV_FREQBAND" "0" + "TXFE_CFG0" "16'b0000001111000010" + "TXFE_CFG1" "16'b0110110000000000" + "TXFE_CFG2" "16'b0110110000000000" + "TXFE_CFG3" "16'b0110110000000000" + "TXPI_CFG0" "16'b0000001100000000" + "TXPI_CFG1" "16'b0001000000000000" + "TXSWBST_EN" "0" + } + + set correction_map { + "TXOUT_DIV" "TX_OUT_DIV" + "RXOUT_DIV" "RX_OUT_DIV" + "CPLL_FBDIV_45" "CPLL_FBDIV_4_5" + "RXCDR_CFG" "RX_CDR_CFG" + } + + set updated_params {} + set param_file_path [dict get $file_paths param_file_path] + set cfng_file_path [dict get $file_paths cfng_file_path] + + if {$param_file_path ne ""} { + + set param_file_content [read [open $param_file_path r]] + + # Define a regex pattern for extracting the value of QPLL_FBDIV_TOP from $param_file_path + set param_pattern {QPLL_FBDIV_TOP = ([0-9]+);} + set match [regexp -inline $param_pattern $param_file_content] + set QPLL_FBDIV_TOP [lindex $match 1] + + switch $QPLL_FBDIV_TOP { + 16 {set QPLL_FBDIV_IN "10'b0000100000"} + 20 {set QPLL_FBDIV_IN "10'b0000110000"} + 32 {set QPLL_FBDIV_IN "10'b0001100000"} + 40 {set QPLL_FBDIV_IN "10'b0010000000"} + 64 {set QPLL_FBDIV_IN "10'b0011100000"} + 66 {set QPLL_FBDIV_IN "10'b0101000000"} + 80 {set QPLL_FBDIV_IN "10'b0100100000"} + 100 {set QPLL_FBDIV_IN "10'b0101110000"} + default {set QPLL_FBDIV_IN "10'b0000000000"} + } + + switch $QPLL_FBDIV_TOP { + 66 {set QPLL_FBDIV_RATIO "1'b0"} + default {set QPLL_FBDIV_RATIO "1'b1"} + } + } + + set file_content [read [open $cfng_file_path r]] + set match "" + regexp {QPLL[0-9]+} $cfng_file_path match + + # Define a regex pattern for extracting parameters and their values + set pattern {'([^']+)' => '([^']+\\?'?[0-9a-hA-H]*)'} + set results {} + set matches [regexp -all -inline $pattern $file_content] + + for {set i 0} {$i < [llength $matches]} {incr i 3} { + + set param [lindex $matches $i+1] + set value [lindex $matches $i+2] + + set cleaned_value [string map {"\\" ""} $value] + set corrected_param $param + + if {[dict exists $correction_map $param]} { + set corrected_param [dict get $correction_map $param] + } + + if {[string first $match $param] == 0} { + + if {[regexp {^(QPLL)[0-9]+(.*)} $param _ prefix rest]} { + set corrected_param "${prefix}${rest}" + } + } + + if {[dict exists $default_parameters $corrected_param]} { + + set default_value [dict get $default_parameters $corrected_param] + + if {$cleaned_value != $default_value} { + + if {[string equal $cleaned_value "QPLL_FBDIV_IN"]} { + set cleaned_value $QPLL_FBDIV_IN + } + if {[string equal $cleaned_value "QPLL_FBDIV_RATIO"]} { + set cleaned_value $QPLL_FBDIV_RATIO + } + if {[string equal $corrected_param "PREIQ_FREQ_BST"]} { + set cleaned_value [expr {$cleaned_value}] + } + + dict set updated_params $corrected_param $cleaned_value + } + } + lappend results [list $corrected_param $cleaned_value] + } + + if {[llength $parameters] > 0} { + foreach {key value} $parameters { + + if {[dict exists $default_parameters $key]} { + set default_value [dict get $default_parameters $key] + + if {$value != $default_value} { + dict set updated_params $key $value + } + } + if {[dict exists $updated_params $key]} { + set default_value [dict get $updated_params $key] + + if {$value != $default_value} { + dict set updated_params $key $value + } + } + } + } + + return $updated_params +} diff --git a/projects/scripts/adi_project_xilinx.tcl b/projects/scripts/adi_project_xilinx.tcl index d29c2eaf752..db276f35019 100644 --- a/projects/scripts/adi_project_xilinx.tcl +++ b/projects/scripts/adi_project_xilinx.tcl @@ -340,6 +340,89 @@ proc adi_project_files {project_name project_files} { set_property top system_top [current_fileset] } +## Function to execute a `make` command for xcvr_wizard project within another project. +# +# \param[project_name] - project name for which you want to run make +# \param[parameters_for_make] - parameters for the make command +# +proc adi_xcvr_project {parameters_for_make} { + + global ad_hdl_dir + + set project_name "xcvr_wizard" + set current_dir [pwd] + set carrier_name [file tail $current_dir] + + switch $carrier_name { + "zc706" { + set xcvr_type GTXE2 + } + "kc705" { + set xcvr_type GTXE2 + } + "zed" { + set xcvr_type GTXE2 + } + "vc707" { + set xcvr_type GTXE2 + } + "kcu105" { + set xcvr_type GTHE3 + } + "zcu102" { + set xcvr_type GTHE4 + } + "vcu118" { + set xcvr_type GTYE4 + } + "vcu128" { + set xcvr_type GTYE4 + } + default { + puts "ERROR adi_project_make: Unsupported carrier (device)." + return 1 + } + } + + set parameters_dir_name {} + set make_command "make" + set adi_project_dir_path [file join $ad_hdl_dir/projects $project_name $carrier_name] + cd $adi_project_dir_path + + if {[llength $parameters_for_make] > 0} { + + set formatted_params {} + + foreach {key value} $parameters_for_make { + + lappend formatted_params "$key=$value" + set key_parsed [string map {"LANE_" "" "_" ""} $key] + set value_parrsed [string map {. _} $value] + set ad_project_make_params($key) $value_parrsed + lappend parameters_dir_name "${key_parsed}${value_parrsed}" + } + + append make_command " " [join $formatted_params " "] + set parameters_dir_name [join $parameters_dir_name "_"] + set config_parser_dir_name "${xcvr_type}_${ad_project_make_params(PLL_TYPE)}_${ad_project_make_params(LANE_RATE)}_${ad_project_make_params(REF_CLK)}" + set file_local_param [string tolower $config_parser_dir_name] + append file_local_param "_common.v" + } + + eval exec $make_command + cd $current_dir + + append adi_project_dir_path "/$parameters_dir_name/${project_name}_${carrier_name}.gen/sources_1/ip/${xcvr_type}_cfng.txt" + set config_dir_path [file dirname $adi_project_dir_path] + + set file_local_param_path "" + if {$xcvr_type == "GTXE2"} { + set file_local_param_path [file join $config_dir_path $config_parser_dir_name $file_local_param] + } + + return [dict create "cfng_file_path" $adi_project_dir_path "param_file_path" $file_local_param_path] +} + ## Run an existing project (generate bit stream). # # \param[project_name] - name of the project diff --git a/projects/scripts/gtwizard_generator.tcl b/projects/scripts/gtwizard_generator.tcl index 11a1d982715..15816092522 100644 --- a/projects/scripts/gtwizard_generator.tcl +++ b/projects/scripts/gtwizard_generator.tcl @@ -486,6 +486,7 @@ proc get_diff_params { {lane_rate_l {}} {pll_type {}} {ref_clk_l {}} {keep_ip " set current_dir [pwd] set project_name [get_property NAME [current_project]] + set hdl_projects_path [file normalize [file join $current_dir "../.."]] ## Generate configurations ad_gth_generator $lane_rate_l $pll_type $ref_clk_l @@ -493,42 +494,49 @@ proc get_diff_params { {lane_rate_l {}} {pll_type {}} {ref_clk_l {}} {keep_ip " ## Call parser script gtwiz_parser.pl cd $project_name\.gen/sources_1/ip # exec $::env(ADI_HDL_DIR)/projects/scripts/gtwiz_parser.pl $gt_type + # exec ../../../../../scripts/gtwiz_parser.pl $gt_type # catch exception for the next line. If it catches something, come back to $current_dir - if { [catch { exec ../../../../../scripts/gtwiz_parser.pl $gt_type } e] } { - cd $current_dir - puts "Some error has occured: \n$e"; - } else { - exec ../../../../../scripts/gtwiz_parser.pl $gt_type - cd $current_dir - - ## if keep_ip not true, remove from the project the generated IPs and delete them - if {$keep_ip ne "true"} { - foreach lane_rate $lane_rate_l { - foreach ref_clk $ref_clk_l { - set lane_rate_txt [string replace $lane_rate [string first . $lane_rate] [string first . $lane_rate] "_"] - set ref_clk_txt [lindex [split $ref_clk "."] 0] - - ## Get the paths to generated IP so that it can be removed - set src_path $current_dir/$project_name\.srcs/sources_1/ip - set gen_path $current_dir/$project_name\.gen/sources_1/ip - set ip_name [eval exec ls $src_path | grep $gt_type\_$pll_type\_$lane_rate_txt\_$ref_clk_txt] - set ip_path_src $src_path\/$ip_name - set ip_path_gen $gen_path\/$ip_name - set xci_file $ip_path_src/$ip_name\.xci - - ## Remove the generated IP after the differences were written - export_ip_user_files -of_objects [get_files $xci_file] -no_script -reset -force -quiet - remove_files -fileset $ip_name $xci_file - file delete -force $ip_path_src - file delete -force $ip_path_gen + set dst_path [pwd] + if {[file tail $dst_path] eq "ip"} { + if { [catch { exec $hdl_projects_path/scripts/gtwiz_parser.pl $gt_type } e] } { + cd $current_dir + puts "Some error has occured: \n$e"; + } else { + exec $hdl_projects_path/scripts/gtwiz_parser.pl $gt_type + cd $current_dir + + ## if keep_ip not true, remove from the project the generated IPs and delete them + if {$keep_ip ne "true"} { + foreach lane_rate $lane_rate_l { + foreach ref_clk $ref_clk_l { + set lane_rate_txt [string replace $lane_rate [string first . $lane_rate] [string first . $lane_rate] "_"] + set ref_clk_txt [lindex [split $ref_clk "."] 0] + + ## Get the paths to generated IP so that it can be removed + set src_path $current_dir/$project_name\.srcs/sources_1/ip + set gen_path $current_dir/$project_name\.gen/sources_1/ip + set ip_name [eval exec ls $src_path | grep $gt_type\_$pll_type\_$lane_rate_txt\_$ref_clk_txt] + set ip_path_src $src_path\/$ip_name + set ip_path_gen $gen_path\/$ip_name + set xci_file $ip_path_src/$ip_name\.xci + + ## Remove the generated IP after the differences were written + export_ip_user_files -of_objects [get_files $xci_file] -no_script -reset -force -quiet + remove_files -fileset $ip_name $xci_file + file delete -force $ip_path_src + file delete -force $ip_path_gen + } } + } else { + puts "\ngenerated files can be find at $project_name\.gen/sources_1/ip" } - } else { - puts "\ngenerated files can be find at $project_name\.gen/sources_1/ip" - } - puts "\nconfiguration file for the tranciever is $project_name\.gen/sources_1/ip/$gt_type\_cfng.txt" + puts "\nconfiguration file for the tranciever is $project_name\.gen/sources_1/ip/$gt_type\_cfng.txt" + } + } else { + puts "For running the parser script you should be in ip directory" } + } From 14dc308519cc8513e6772ea27fb63afebe660033 Mon Sep 17 00:00:00 2001 From: Elena-Hadarau_adi Date: Thu, 27 Mar 2025 14:44:31 +0200 Subject: [PATCH 3/3] projects: Integrate xcvr automation Signed-off-by: Elena-Hadarau_adi --- projects/adrv9009/common/adrv9009_bd.tcl | 19 +++++------ projects/adrv9009/zc706/system_project.tcl | 27 +++++++++++++--- projects/adrv9009/zcu102/system_bd.tcl | 4 +-- projects/adrv9009/zcu102/system_project.tcl | 26 +++++++++++++-- projects/adrv9026/common/adrv9026_bd.tcl | 33 +++++++++----------- projects/adrv9026/vcu118/system_project.tcl | 26 +++++++++++++++ projects/adrv9026/zcu102/system_project.tcl | 32 ++++++++++++++++++- projects/adrv9371x/common/adrv9371x_bd.tcl | 20 ++++++------ projects/adrv9371x/kcu105/system_bd.tcl | 6 ---- projects/adrv9371x/kcu105/system_project.tcl | 24 +++++++++++++- projects/adrv9371x/zc706/system_project.tcl | 24 +++++++++++++- projects/adrv9371x/zcu102/system_bd.tcl | 2 -- projects/adrv9371x/zcu102/system_project.tcl | 24 +++++++++++++- projects/daq2/common/daq2_bd.tcl | 18 +++++------ projects/daq2/kc705/system_project.tcl | 24 +++++++++++++- projects/daq2/kcu105/system_bd.tcl | 6 ---- projects/daq2/kcu105/system_project.tcl | 24 +++++++++++++- projects/daq2/zc706/system_project.tcl | 24 +++++++++++++- projects/daq2/zcu102/system_bd.tcl | 5 +-- projects/daq2/zcu102/system_project.tcl | 24 +++++++++++++- projects/daq3/common/daq3_bd.tcl | 19 ++++++----- projects/daq3/kcu105/system_bd.tcl | 8 ++--- projects/daq3/kcu105/system_project.tcl | 27 ++++++++++++++-- projects/daq3/vcu118/system_bd.tcl | 16 ---------- projects/daq3/vcu118/system_project.tcl | 24 +++++++++++++- projects/daq3/zc706/system_project.tcl | 24 +++++++++++++- projects/daq3/zcu102/system_bd.tcl | 3 -- projects/daq3/zcu102/system_project.tcl | 24 +++++++++++++- 28 files changed, 414 insertions(+), 123 deletions(-) diff --git a/projects/adrv9009/common/adrv9009_bd.tcl b/projects/adrv9009/common/adrv9009_bd.tcl index 7bd8c6c0bbc..05bb990ad77 100644 --- a/projects/adrv9009/common/adrv9009_bd.tcl +++ b/projects/adrv9009/common/adrv9009_bd.tcl @@ -17,6 +17,7 @@ set DATAPATH_WIDTH 4 source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl +source $ad_hdl_dir/library/xilinx/scripts/xcvr_automation.tcl # TX parameters set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L @@ -221,18 +222,14 @@ ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY # common cores +global xcvr_config_paths -ad_ip_instance util_adxcvr util_adrv9009_xcvr -ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_NUM_OF_LANES [expr $MAX_RX_NUM_OF_LANES+$MAX_RX_OS_NUM_OF_LANES] -ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES -ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_OUT_DIV 1 -ad_ip_parameter util_adrv9009_xcvr CONFIG.CPLL_FBDIV 4 -ad_ip_parameter util_adrv9009_xcvr CONFIG.CPLL_FBDIV_4_5 5 -ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_CLK25_DIV 10 -ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_CLK25_DIV 10 -ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_PMA_CFG 0x001E7080 -ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020 -ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 0x080 +set util_adxcvr_parameters [adi_xcvr_parameters $xcvr_config_paths [list \ + RX_NUM_OF_LANES [expr $MAX_RX_NUM_OF_LANES+$MAX_RX_OS_NUM_OF_LANES] \ + TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES\ +]] + +ad_ip_instance util_adxcvr util_adrv9009_xcvr $util_adxcvr_parameters # xcvr interfaces diff --git a/projects/adrv9009/zc706/system_project.tcl b/projects/adrv9009/zc706/system_project.tcl index 145d2f0fb09..bb984d7461c 100644 --- a/projects/adrv9009/zc706/system_project.tcl +++ b/projects/adrv9009/zc706/system_project.tcl @@ -13,9 +13,29 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make TX_JESD_L=2 RX_OS_JESD_M=4 -# make TX_JESD_M=4 TX_JESD_L=2 RX_JESD_M=4 RX_JESD_L=1 RX_OS_JESD_M=2 RX_OS_JESD_L=1 -# make TX_JESD_M=2 TX_JESD_L=1 RX_JESD_M=4 RX_JESD_L=1 RX_OS_JESD_M=2 RX_OS_JESD_L=1 +# make PLL_TYPE=CPLL REF_CLK=125 LANE_RATE=5 + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL] +# +# e.g. call for make with parameters +# set xcvr_config_paths [adi_xcvr_project [list \ +# LANE_RATE 5\ +# REF_CLK 125\ +# PLL_TYPE CPLL\ +# ]] +# The function returns a dictionary with the paths to the `cfng` file +# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2. + +global xcvr_config_paths + +set xcvr_config_paths [adi_xcvr_project [list \ + LANE_RATE [get_env_param LANE_RATE 5] \ + REF_CLK [get_env_param REF_CLK 125] \ + PLL_TYPE [get_env_param PLL_TYPE CPLL] \ +]] # Parameter description: # [TX/RX/RX_OS]_JESD_M : Number of converters per link @@ -46,4 +66,3 @@ adi_project_files adrv9009_zc706 [list \ adi_project_run adrv9009_zc706 - diff --git a/projects/adrv9009/zcu102/system_bd.tcl b/projects/adrv9009/zcu102/system_bd.tcl index ad03b5a4649..97aa70e1c8c 100644 --- a/projects/adrv9009/zcu102/system_bd.tcl +++ b/projects/adrv9009/zcu102/system_bd.tcl @@ -41,5 +41,5 @@ ad_ip_parameter axi_adrv9009_rx_dma CONFIG.FIFO_SIZE 32 ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.FIFO_SIZE 32 ad_ip_parameter axi_adrv9009_tx_dma CONFIG.FIFO_SIZE 32 -ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 80 -ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_REFCLK_DIV 1 +# ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 80 +# ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_REFCLK_DIV 1 diff --git a/projects/adrv9009/zcu102/system_project.tcl b/projects/adrv9009/zcu102/system_project.tcl index f00400197d0..57641f48fe3 100644 --- a/projects/adrv9009/zcu102/system_project.tcl +++ b/projects/adrv9009/zcu102/system_project.tcl @@ -13,9 +13,29 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make TX_JESD_L=2 RX_OS_JESD_M=4 -# make TX_JESD_M=4 TX_JESD_L=2 RX_JESD_M=4 RX_JESD_L=1 RX_OS_JESD_M=2 RX_OS_JESD_L=1 -# make TX_JESD_M=2 TX_JESD_L=1 RX_JESD_M=4 RX_JESD_L=1 RX_OS_JESD_M=2 RX_OS_JESD_L=1 +# make PLL_TYPE=QPLL0 REF_CLK=250 LANE_RATE=10 + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL0/QPLL1] +# +# e.g. call for make with parameters +# set xcvr_config_paths [adi_xcvr_project [list \ +# LANE_RATE 10\ +# REF_CLK 250\ +# PLL_TYPE QPLL0\ +# ]] +# The function returns a dictionary with the paths to the `cfng` file +# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2. + +global xcvr_config_paths + +set xcvr_config_paths [adi_xcvr_project [list \ + LANE_RATE [get_env_param LANE_RATE 10] \ + REF_CLK [get_env_param REF_CLK 250] \ + PLL_TYPE [get_env_param PLL_TYPE QPLL0] \ +]] # Parameter description: # [TX/RX/RX_OS]_JESD_M : Number of converters per link diff --git a/projects/adrv9026/common/adrv9026_bd.tcl b/projects/adrv9026/common/adrv9026_bd.tcl index d81f556827c..618390aadcc 100644 --- a/projects/adrv9026/common/adrv9026_bd.tcl +++ b/projects/adrv9026/common/adrv9026_bd.tcl @@ -140,24 +140,21 @@ create_bd_port -dir I $rx_ref_clk # common cores -ad_ip_instance util_adxcvr util_adrv9026_xcvr -ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES -ad_ip_parameter util_adrv9026_xcvr CONFIG.LINK_MODE $ENCODER_SEL -ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE -ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE -ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_OUT_DIV 1 -ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES -ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_OUT_DIV 1 -ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV 4 -ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV_4_5 5 -ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CLK25_DIV 10 -ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_CLK25_DIV 10 -ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_PMA_CFG 0x001E7080 -ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020 -ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_FBDIV 40 -ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_REFCLK_DIV 1 -ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_INVERT 6 -ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_INVERT 15 +source $ad_hdl_dir/library/xilinx/scripts/xcvr_automation.tcl + +global xcvr_config_paths + +set util_adxcvr_parameters [adi_xcvr_parameters $xcvr_config_paths [list \ + LINK_MODE $ENCODER_SEL \ + RX_LANE_RATE $RX_LANE_RATE \ + TX_LANE_RATE $TX_LANE_RATE \ + TX_LANE_INVERT 6 \ + RX_LANE_INVERT 15 \ + RX_NUM_OF_LANES $RX_NUM_OF_LANES \ + TX_NUM_OF_LANES $TX_NUM_OF_LANES\ +]] + +ad_ip_instance util_adxcvr util_adrv9026_xcvr $util_adxcvr_parameters ad_connect $sys_cpu_resetn util_adrv9026_xcvr/up_rstn ad_connect $sys_cpu_clk util_adrv9026_xcvr/up_clk diff --git a/projects/adrv9026/vcu118/system_project.tcl b/projects/adrv9026/vcu118/system_project.tcl index 39801fcbaae..8b317b63bca 100644 --- a/projects/adrv9026/vcu118/system_project.tcl +++ b/projects/adrv9026/vcu118/system_project.tcl @@ -12,6 +12,31 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # # Use over-writable parameters from the environment. # +# e.g. +# make PLL_TYPE=QPLL0 REF_CLK=245.75 LANE_RATE=9.83 + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL0/QPLL1] +# +# e.g. call for make with parameters +# set xcvr_config_paths [adi_xcvr_project [list \ +# LANE_RATE 9.83\ +# REF_CLK 245.75\ +# PLL_TYPE QPLL0\ +# ]] +# The function returns a dictionary with the paths to the `cfng` file +# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2. + +global xcvr_config_paths + +set xcvr_config_paths [adi_xcvr_project [list \ + LANE_RATE [get_env_param LANE_RATE 9.83] \ + REF_CLK [get_env_param REF_CLK 245.75] \ + PLL_TYPE [get_env_param PLL_TYPE QPLL0] \ +]] + # Parameter description: # [TX/RX/RX_OS]_JESD_M : Number of converters per link # [TX/RX/RX_OS]_JESD_L : Number of lanes per link @@ -41,3 +66,4 @@ adi_project_files adrv9026_vcu118 [list \ ## To improve timing of the BRAM buffers adi_project_run adrv9026_vcu118 + diff --git a/projects/adrv9026/zcu102/system_project.tcl b/projects/adrv9026/zcu102/system_project.tcl index a1526cdd2b4..3d852dee5d5 100644 --- a/projects/adrv9026/zcu102/system_project.tcl +++ b/projects/adrv9026/zcu102/system_project.tcl @@ -7,6 +7,36 @@ source ../../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# make PLL_TYPE=QPLL0 REF_CLK=245.75 LANE_RATE=9.83 + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL0/QPLL1] +# +# e.g. call for make with parameters +# set xcvr_config_paths [adi_xcvr_project [list \ +# LANE_RATE 9.83\ +# REF_CLK 245.75\ +# PLL_TYPE QPLL0\ +# ]] +# The function returns a dictionary with the paths to the `cfng` file +# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2. + +global xcvr_config_paths + +set xcvr_config_paths [adi_xcvr_project [list \ + LANE_RATE [get_env_param LANE_RATE 9.83] \ + REF_CLK [get_env_param REF_CLK 245.75] \ + PLL_TYPE [get_env_param PLL_TYPE QPLL0] \ +]] + adi_project adrv9026_zcu102 0 [list \ JESD_MODE [get_env_param JESD_MODE 8B10B ] \ TX_LANE_RATE [get_env_param TX_LANE_RATE 9.83 ] \ @@ -26,4 +56,4 @@ adi_project_files adrv9026_zcu102 [list \ "$ad_hdl_dir/library/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] -adi_project_run adrv9026_zcu102 \ No newline at end of file +adi_project_run adrv9026_zcu102 diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl index 2f81021a879..73a94be0cfc 100644 --- a/projects/adrv9371x/common/adrv9371x_bd.tcl +++ b/projects/adrv9371x/common/adrv9371x_bd.tcl @@ -47,6 +47,7 @@ set dac_dma_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMP source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl +source $ad_hdl_dir/library/xilinx/scripts/xcvr_automation.tcl # ad9371 @@ -203,16 +204,14 @@ ad_ip_parameter axi_ad9371_rx_os_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY # common cores -ad_ip_instance util_adxcvr util_ad9371_xcvr -ad_ip_parameter util_ad9371_xcvr CONFIG.RX_NUM_OF_LANES [expr $MAX_RX_NUM_OF_LANES+$MAX_RX_OS_NUM_OF_LANES] -ad_ip_parameter util_ad9371_xcvr CONFIG.TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES -ad_ip_parameter util_ad9371_xcvr CONFIG.TX_OUT_DIV 2 -ad_ip_parameter util_ad9371_xcvr CONFIG.CPLL_FBDIV 4 -ad_ip_parameter util_ad9371_xcvr CONFIG.RX_CLK25_DIV 5 -ad_ip_parameter util_ad9371_xcvr CONFIG.TX_CLK25_DIV 5 -ad_ip_parameter util_ad9371_xcvr CONFIG.RX_PMA_CFG 0x00018480 -ad_ip_parameter util_ad9371_xcvr CONFIG.RX_CDR_CFG 0x03000023ff20400020 -ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_FBDIV 0x120 +global xcvr_config_paths + +set util_adxcvr_parameters [adi_xcvr_parameters $xcvr_config_paths [list \ + RX_NUM_OF_LANES [expr $MAX_RX_NUM_OF_LANES+$MAX_RX_OS_NUM_OF_LANES] \ + TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES\ +]] + +ad_ip_instance util_adxcvr util_ad9371_xcvr $util_adxcvr_parameters # xcvr interfaces @@ -410,3 +409,4 @@ ad_cpu_interrupt ps-10 mb-15 axi_ad9371_rx_jesd/irq ad_cpu_interrupt ps-11 mb-14 axi_ad9371_rx_os_dma/irq ad_cpu_interrupt ps-12 mb-13- axi_ad9371_tx_dma/irq ad_cpu_interrupt ps-13 mb-12 axi_ad9371_rx_dma/irq + diff --git a/projects/adrv9371x/kcu105/system_bd.tcl b/projects/adrv9371x/kcu105/system_bd.tcl index 9908aa2e912..fc730c06d4f 100644 --- a/projects/adrv9371x/kcu105/system_bd.tcl +++ b/projects/adrv9371x/kcu105/system_bd.tcl @@ -34,9 +34,3 @@ sysid_gen_sys_init_file $sys_cstring ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ 200 source ../common/adrv9371x_bd.tcl - -ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_FBDIV 80 -ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_REFCLK_DIV 1 -ad_ip_parameter util_ad9371_xcvr CONFIG.CPLL_CFG0 0x67f8 -ad_ip_parameter util_ad9371_xcvr CONFIG.CPLL_CFG1 0xa4ac -ad_ip_parameter util_ad9371_xcvr CONFIG.CPLL_CFG2 0x0007 diff --git a/projects/adrv9371x/kcu105/system_project.tcl b/projects/adrv9371x/kcu105/system_project.tcl index 7b41a6081c2..968e6be79a6 100644 --- a/projects/adrv9371x/kcu105/system_project.tcl +++ b/projects/adrv9371x/kcu105/system_project.tcl @@ -13,7 +13,29 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 +# make PLL_TYPE=CPLL REF_CLK=125 LANE_RATE=5 + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL0/QPLL1] +# +# e.g. call for make with parameters +# set xcvr_config_paths [adi_xcvr_project [list \ +# LANE_RATE 5\ +# REF_CLK 125\ +# PLL_TYPE CPLL\ +# ]] +# The function returns a dictionary with the paths to the `cfng` file +# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2. + +global xcvr_config_paths + +set xcvr_config_paths [adi_xcvr_project [list \ + LANE_RATE [get_env_param LANE_RATE 5] \ + REF_CLK [get_env_param REF_CLK 125] \ + PLL_TYPE [get_env_param PLL_TYPE CPLL] \ +]] # Parameter description: # [TX/RX/RX_OS]_JESD_M : Number of converters per link diff --git a/projects/adrv9371x/zc706/system_project.tcl b/projects/adrv9371x/zc706/system_project.tcl index 3db6672ac57..1bd5bc34bc4 100644 --- a/projects/adrv9371x/zc706/system_project.tcl +++ b/projects/adrv9371x/zc706/system_project.tcl @@ -13,7 +13,29 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 +# make PLL_TYPE=CPLL REF_CLK=125 LANE_RATE=5 + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL] +# +# e.g. call for make with parameters +# set xcvr_config_paths [adi_xcvr_project [list \ +# LANE_RATE 5\ +# REF_CLK 125\ +# PLL_TYPE CPLL\ +# ]] +# The function returns a dictionary with the paths to the `cfng` file +# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2. + +global xcvr_config_paths + +set xcvr_config_paths [adi_xcvr_project [list \ + LANE_RATE [get_env_param LANE_RATE 5] \ + REF_CLK [get_env_param REF_CLK 125] \ + PLL_TYPE [get_env_param PLL_TYPE CPLL] \ +]] # Parameter description: # [TX/RX/RX_OS]_JESD_M : Number of converters per link diff --git a/projects/adrv9371x/zcu102/system_bd.tcl b/projects/adrv9371x/zcu102/system_bd.tcl index 963fedecf6e..702c24ea0b0 100644 --- a/projects/adrv9371x/zcu102/system_bd.tcl +++ b/projects/adrv9371x/zcu102/system_bd.tcl @@ -38,5 +38,3 @@ source ../common/adrv9371x_bd.tcl ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.TX_DIFFCTRL 6 -ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_FBDIV 80 -ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_REFCLK_DIV 1 diff --git a/projects/adrv9371x/zcu102/system_project.tcl b/projects/adrv9371x/zcu102/system_project.tcl index e0f1ae342fb..0f4632d940e 100644 --- a/projects/adrv9371x/zcu102/system_project.tcl +++ b/projects/adrv9371x/zcu102/system_project.tcl @@ -13,7 +13,29 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 +# make PLL_TYPE=CPLL REF_CLK=125 LANE_RATE=5 + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL0/QPLL1] +# +# e.g. call for make with parameters +# set xcvr_config_paths [adi_xcvr_project [list \ +# LANE_RATE 5\ +# REF_CLK 125\ +# PLL_TYPE CPLL\ +# ]] +# The function returns a dictionary with the paths to the `cfng` file +# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2. + +global xcvr_config_paths + +set xcvr_config_paths [adi_xcvr_project [list \ + LANE_RATE [get_env_param LANE_RATE 5] \ + REF_CLK [get_env_param REF_CLK 125] \ + PLL_TYPE [get_env_param PLL_TYPE CPLL] \ +]] # Parameter description: # [TX/RX/RX_OS]_JESD_M : Number of converters per link diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index 9a7084d6380..c49e3deaec9 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -12,6 +12,7 @@ source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl +source $ad_hdl_dir/library/xilinx/scripts/xcvr_automation.tcl # JESD204B interface configurations @@ -133,17 +134,14 @@ ad_connect axi_ad9680_offload/sync_ext GND # shared transceiver core -ad_ip_instance util_adxcvr util_daq2_xcvr [list \ +global xcvr_config_paths + +set util_adxcvr_parameters [adi_xcvr_parameters $xcvr_config_paths [list \ RX_NUM_OF_LANES $MAX_RX_NUM_OF_LANES \ - TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES \ - QPLL_REFCLK_DIV 1 \ - QPLL_FBDIV_RATIO 1 \ - QPLL_FBDIV 0x30 \ - RX_OUT_DIV 1 \ - TX_OUT_DIV 1 \ - RX_DFE_LPM_CFG 0x0104 \ - RX_CDR_CFG 0x0B000023FF10400020 \ -] + TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES\ +]] + +ad_ip_instance util_adxcvr util_daq2_xcvr $util_adxcvr_parameters ad_connect $sys_cpu_resetn util_daq2_xcvr/up_rstn ad_connect $sys_cpu_clk util_daq2_xcvr/up_clk diff --git a/projects/daq2/kc705/system_project.tcl b/projects/daq2/kc705/system_project.tcl index e561303e50a..b2853575985 100644 --- a/projects/daq2/kc705/system_project.tcl +++ b/projects/daq2/kc705/system_project.tcl @@ -13,7 +13,29 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 +# make PLL_TYPE=QPLL REF_CLK=500 LANE_RATE=10 + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL] +# +# e.g. call for make with parameters +# set xcvr_config_paths [adi_xcvr_project [list \ +# LANE_RATE 10\ +# REF_CLK 500\ +# PLL_TYPE QPLL\ +# ]] +# The function returns a dictionary with the paths to the `cfng` file +# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2. + +global xcvr_config_paths + +set xcvr_config_paths [adi_xcvr_project [list \ + LANE_RATE [get_env_param LANE_RATE 10]\ + REF_CLK [get_env_param REF_CLK 500]\ + PLL_TYPE [get_env_param PLL_TYPE QPLL]\ +]] # Parameter description: # [RX/TX]_JESD_M : Number of converters per link diff --git a/projects/daq2/kcu105/system_bd.tcl b/projects/daq2/kcu105/system_bd.tcl index a7f93d16a25..45ca30f6670 100644 --- a/projects/daq2/kcu105/system_bd.tcl +++ b/projects/daq2/kcu105/system_bd.tcl @@ -35,9 +35,3 @@ DAC_OFFLOAD:TYPE=$dac_offload_type\ SIZE=$dac_offload_size" sysid_gen_sys_init_file $sys_cstring - -ad_ip_parameter util_daq2_xcvr CONFIG.QPLL_FBDIV 20 -ad_ip_parameter util_daq2_xcvr CONFIG.QPLL_REFCLK_DIV 1 -ad_ip_parameter util_daq2_xcvr CONFIG.CPLL_CFG0 0x67f8 -ad_ip_parameter util_daq2_xcvr CONFIG.CPLL_CFG1 0xa4ac -ad_ip_parameter util_daq2_xcvr CONFIG.CPLL_CFG2 0x0007 diff --git a/projects/daq2/kcu105/system_project.tcl b/projects/daq2/kcu105/system_project.tcl index 9284e46526b..c38f2bd97d2 100644 --- a/projects/daq2/kcu105/system_project.tcl +++ b/projects/daq2/kcu105/system_project.tcl @@ -13,7 +13,29 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 +# make PLL_TYPE=QPLL0 REF_CLK=500 LANE_RATE=10 + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL0/QPLL1] +# +# e.g. call for make with parameters +# set xcvr_config_paths [adi_xcvr_project [list \ +# LANE_RATE 10\ +# REF_CLK 500\ +# PLL_TYPE QPLL0\ +# ]] +# The function returns a dictionary with the paths to the `cfng` file +# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2. + +global xcvr_config_paths + +set xcvr_config_paths [adi_xcvr_project [list \ + LANE_RATE [get_env_param LANE_RATE 10]\ + REF_CLK [get_env_param REF_CLK 500]\ + PLL_TYPE [get_env_param PLL_TYPE QPLL0]\ +]] # Parameter description: # [RX/TX]_JESD_M : Number of converters per link diff --git a/projects/daq2/zc706/system_project.tcl b/projects/daq2/zc706/system_project.tcl index 21f32519ce6..27053cebc88 100644 --- a/projects/daq2/zc706/system_project.tcl +++ b/projects/daq2/zc706/system_project.tcl @@ -13,7 +13,29 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 +# make PLL_TYPE=QPLL REF_CLK=500 LANE_RATE=10 + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL] +# +# e.g. call for make with parameters +# set xcvr_config_paths [adi_xcvr_project [list \ +# LANE_RATE 10\ +# REF_CLK 500\ +# PLL_TYPE QPLL\ +# ]] +# The function returns a dictionary with the paths to the `cfng` file +# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2. + +global xcvr_config_paths + +set xcvr_config_paths [adi_xcvr_project [list \ + LANE_RATE [get_env_param LANE_RATE 10]\ + REF_CLK [get_env_param REF_CLK 500]\ + PLL_TYPE [get_env_param PLL_TYPE QPLL]\ +]] # Parameter description: # [RX/TX]_JESD_M : Number of converters per link diff --git a/projects/daq2/zcu102/system_bd.tcl b/projects/daq2/zcu102/system_bd.tcl index 01cc8b58221..d74d1736f51 100644 --- a/projects/daq2/zcu102/system_bd.tcl +++ b/projects/daq2/zcu102/system_bd.tcl @@ -34,7 +34,4 @@ SIZE=$adc_offload_size\ DAC_OFFLOAD:TYPE=$dac_offload_type\ SIZE=$dac_offload_size" -sysid_gen_sys_init_file $sys_cstring - -ad_ip_parameter util_daq2_xcvr CONFIG.QPLL_FBDIV 20 -ad_ip_parameter util_daq2_xcvr CONFIG.QPLL_REFCLK_DIV 1 +sysid_gen_sys_init_file $sys_cstring \ No newline at end of file diff --git a/projects/daq2/zcu102/system_project.tcl b/projects/daq2/zcu102/system_project.tcl index cdc8af46cef..da77db131f7 100644 --- a/projects/daq2/zcu102/system_project.tcl +++ b/projects/daq2/zcu102/system_project.tcl @@ -13,7 +13,29 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 +# make PLL_TYPE=QPLL0 REF_CLK=500 LANE_RATE=10 + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL0/QPLL1] +# +# e.g. call for make with parameters +# set xcvr_config_paths [adi_xcvr_project [list \ +# LANE_RATE 10\ +# REF_CLK 500\ +# PLL_TYPE QPLL0\ +# ]] +# The function returns a dictionary with the paths to the `cfng` file +# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2. + +global xcvr_config_paths + +set xcvr_config_paths [adi_xcvr_project [list \ + LANE_RATE [get_env_param LANE_RATE 10]\ + REF_CLK [get_env_param REF_CLK 500]\ + PLL_TYPE [get_env_param PLL_TYPE QPLL0]\ +]] # Parameter description: # [RX/TX]_JESD_M : Number of converters per link diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index b2e269e21ab..3769ada3f3c 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -11,6 +11,7 @@ # source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl +source $ad_hdl_dir/library/xilinx/scripts/xcvr_automation.tcl # TX parameters set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L @@ -116,16 +117,14 @@ if {$sys_zynq == 0 || $sys_zynq == 1} { # shared transceiver core -ad_ip_instance util_adxcvr util_daq3_xcvr -ad_ip_parameter util_daq3_xcvr CONFIG.RX_NUM_OF_LANES $MAX_RX_NUM_OF_LANES -ad_ip_parameter util_daq3_xcvr CONFIG.TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1 -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV_RATIO 1 -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 0x30; # 20 -ad_ip_parameter util_daq3_xcvr CONFIG.RX_OUT_DIV 1 -ad_ip_parameter util_daq3_xcvr CONFIG.TX_OUT_DIV 1 -ad_ip_parameter util_daq3_xcvr CONFIG.RX_DFE_LPM_CFG 0x0904 -ad_ip_parameter util_daq3_xcvr CONFIG.RX_CDR_CFG 0x0B000023FF10400020 +global xcvr_config_paths + +set util_adxcvr_parameters [adi_xcvr_parameters $xcvr_config_paths [list \ + RX_NUM_OF_LANES $MAX_RX_NUM_OF_LANES \ + TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES \ +]] + +ad_ip_instance util_adxcvr util_daq3_xcvr $util_adxcvr_parameters ad_connect $sys_cpu_resetn util_daq3_xcvr/up_rstn ad_connect $sys_cpu_clk util_daq3_xcvr/up_clk diff --git a/projects/daq3/kcu105/system_bd.tcl b/projects/daq3/kcu105/system_bd.tcl index 843c4d4d536..448d2184e40 100644 --- a/projects/daq3/kcu105/system_bd.tcl +++ b/projects/daq3/kcu105/system_bd.tcl @@ -33,8 +33,6 @@ DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width" sysid_gen_sys_init_file $sys_cstring -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 20 -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1 -ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG0 0x67f8 -ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG1 0xa4ac -ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG2 0x0007 +ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 128 +ad_ip_parameter axi_ad9680_dma CONFIG.FIFO_SIZE 32 +ad_ip_parameter axi_ad9680_dma CONFIG.MAX_BYTES_PER_BURST 4096 diff --git a/projects/daq3/kcu105/system_project.tcl b/projects/daq3/kcu105/system_project.tcl index d9c1efb1a1c..bb304e54ff9 100644 --- a/projects/daq3/kcu105/system_project.tcl +++ b/projects/daq3/kcu105/system_project.tcl @@ -13,7 +13,29 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 +# make PLL_TYPE=QPLL0 REF_CLK=616.5 LANE_RATE=12.33 + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL0/QPLL1] +# +# e.g. call for make with parameters +# set xcvr_config_paths [adi_xcvr_project [list \ +# LANE_RATE 12.33\ +# REF_CLK 616.5\ +# PLL_TYPE QPLL0\ +# ]] +# The function returns a dictionary with the paths to the `cfng` file +# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2. + +global xcvr_config_paths + +set xcvr_config_paths [adi_xcvr_project [list \ + LANE_RATE [get_env_param LANE_RATE 12.33] \ + REF_CLK [get_env_param REF_CLK 616.5] \ + PLL_TYPE [get_env_param PLL_TYPE QPLL0] \ +]] # Parameter description: # [RX/TX]_JESD_M : Number of converters per link @@ -37,7 +59,8 @@ adi_project_files daq3_kcu105 [list \ "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ] ## To improve timing in DDR4 MIG -set_property strategy Performance_ExploreWithRemap [get_runs impl_1] +set_property strategy Performance_RefinePlacement [get_runs impl_1] +#set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE ExploreWithAggressiveHoldFix [get_runs impl_1] adi_project_run daq3_kcu105 diff --git a/projects/daq3/vcu118/system_bd.tcl b/projects/daq3/vcu118/system_bd.tcl index 8e199ffeb81..816e1011691 100644 --- a/projects/daq3/vcu118/system_bd.tcl +++ b/projects/daq3/vcu118/system_bd.tcl @@ -31,22 +31,6 @@ DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width" sysid_gen_sys_init_file $sys_cstring -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 20 -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1 -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_CFG0 0x331C -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_CFG1 0xD038 -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_CFG2 0xFC1 -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_CFG3 0x120 -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_CFG4 0x2 -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_CFG1_G3 0xD038 -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_CFG2_G3 0xFC1 - -ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG0 0x3fe -ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG1 0x29 -ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG2 0x203 -ad_ip_parameter util_daq3_xcvr CONFIG.RX_CLK25_DIV 25 -ad_ip_parameter util_daq3_xcvr CONFIG.TX_CLK25_DIV 25 - ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST true ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC true ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_DEST true diff --git a/projects/daq3/vcu118/system_project.tcl b/projects/daq3/vcu118/system_project.tcl index 3323ca56464..3ccc8f0ca55 100644 --- a/projects/daq3/vcu118/system_project.tcl +++ b/projects/daq3/vcu118/system_project.tcl @@ -13,7 +13,29 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 +# make PLL_TYPE=QPLL0 REF_CLK=625 LANE_RATE=12.5 + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL0/QPLL1] +# +# e.g. call for make with parameters +# set xcvr_config_paths [adi_xcvr_project [list \ +# LANE_RATE 12.5\ +# REF_CLK 625\ +# PLL_TYPE QPLL0\ +# ]] +# The function returns a dictionary with the paths to the `cfng` file +# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2. + +global xcvr_config_paths + +set xcvr_config_paths [adi_xcvr_project [list \ + LANE_RATE [get_env_param LANE_RATE 12.5] \ + REF_CLK [get_env_param REF_CLK 625] \ + PLL_TYPE [get_env_param PLL_TYPE QPLL0] \ +]] # Parameter description: # [RX/TX]_JESD_M : Number of converters per link diff --git a/projects/daq3/zc706/system_project.tcl b/projects/daq3/zc706/system_project.tcl index b387c9cf092..9815d3afa93 100644 --- a/projects/daq3/zc706/system_project.tcl +++ b/projects/daq3/zc706/system_project.tcl @@ -13,7 +13,29 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 +# make PLL_TYPE=QPLL REF_CLK=500 LANE_RATE=10 + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL] +# +# e.g. call for make with parameters +# set xcvr_config_paths [adi_xcvr_project [list \ +# LANE_RATE 10\ +# REF_CLK 500\ +# PLL_TYPE QPLL\ +# ]] +# The function returns a dictionary with the paths to the `cfng` file +# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2. + +global xcvr_config_paths + +set xcvr_config_paths [adi_xcvr_projec [list \ + LANE_RATE [get_env_param LANE_RATE 10] \ + REF_CLK [get_env_param REF_CLK 500] \ + PLL_TYPE [get_env_param PLL_TYPE QPLL] \ +]] # Parameter description: # [RX/TX]_JESD_M : Number of converters per link diff --git a/projects/daq3/zcu102/system_bd.tcl b/projects/daq3/zcu102/system_bd.tcl index 613b8c01bd6..daa0e959e59 100644 --- a/projects/daq3/zcu102/system_bd.tcl +++ b/projects/daq3/zcu102/system_bd.tcl @@ -35,9 +35,6 @@ ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG2 0x0203 create_bd_port -dir I dac_fifo_bypass -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 20 -ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1 - ad_ip_parameter axi_ad9152_dma CONFIG.FIFO_SIZE 32 ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_SRC 1 ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_DEST 1 diff --git a/projects/daq3/zcu102/system_project.tcl b/projects/daq3/zcu102/system_project.tcl index 8cf3c30f390..c707186c38a 100644 --- a/projects/daq3/zcu102/system_project.tcl +++ b/projects/daq3/zcu102/system_project.tcl @@ -13,7 +13,29 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 +# make PLL_TYPE=QPLL0 REF_CLK=616.5 LANE_RATE=12.33 + +# Parameter description: +# LANE_RATE: Value of lane rate [gbps] +# REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40) +# PLL_TYPE: The PLL used for driving the link [CPLL/QPLL0/QPLL1] +# +# e.g. call for make with parameters +# set xcvr_config_paths [adi_xcvr_project [list \ +# LANE_RATE 12.33\ +# REF_CLK 616.5\ +# PLL_TYPE QPLL0\ +# ]] +# The function returns a dictionary with the paths to the `cfng` file +# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2. + +global xcvr_config_paths + +set xcvr_config_paths [adi_xcvr_project [list \ + LANE_RATE [get_env_param LANE_RATE 12.33] \ + REF_CLK [get_env_param REF_CLK 616.5] \ + PLL_TYPE [get_env_param PLL_TYPE QPLL0] \ +]] # Parameter description: # [RX/TX]_JESD_M : Number of converters per link