-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathLAB_4.gise
223 lines (210 loc) · 14.2 KB
/
LAB_4.gise
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="LAB_4.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="carry_calc.prj"/>
<file xil_pn:fileType="FILE_XST_STX" xil_pn:name="carry_calc.stx"/>
<file xil_pn:fileType="FILE_XST" xil_pn:name="carry_calc.xst"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="carry_lookahead_adder.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="carry_lookahead_adder.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="carry_lookahead_adder.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="carry_lookahead_adder.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="carry_lookahead_adder.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="carry_lookahead_adder.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="carry_lookahead_adder.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="carry_lookahead_adder.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="carry_lookahead_adder_summary.html"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="carry_lookahead_adder_testbench_isim_beh.exe"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="carry_lookahead_adder_testbench_stx_beh.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="carry_lookahead_adder_xst.xrpt"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="carry_select_adder.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="carry_select_adder.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="carry_select_adder.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="carry_select_adder.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="carry_select_adder.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="carry_select_adder.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="carry_select_adder.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="carry_select_adder.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="carry_select_adder_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="carry_select_adder_testbench_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="carry_select_adder_testbench_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="carry_select_adder_testbench_isim_beh.wdb"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="carry_select_adder_testbench_stx_beh.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="carry_select_adder_xst.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="full_adder.ngr"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="mux_2to1.prj"/>
<file xil_pn:fileType="FILE_XST_STX" xil_pn:name="mux_2to1.stx"/>
<file xil_pn:fileType="FILE_XST" xil_pn:name="mux_2to1.xst"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="ripple_adder.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="ripple_adder.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="ripple_adder.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="ripple_adder.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ripple_adder.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="ripple_adder.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="ripple_adder.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="ripple_adder.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="ripple_adder_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="ripple_adder_summary.html"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="ripple_adder_testbech_isim_beh.exe"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ripple_adder_testbech_stx_beh.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ripple_adder_testbench_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="ripple_adder_testbench_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="ripple_adder_testbench_isim_beh.wdb"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ripple_adder_testbench_stx_beh.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="ripple_adder_xst.xrpt"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1598533770" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1598533770">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598533770" xil_pn:in_ck="9127768792623154011" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1598533770">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="and_gate.vhd"/>
<outfile xil_pn:name="carry_calc.vhd"/>
<outfile xil_pn:name="carry_lookahead_adder.vhd"/>
<outfile xil_pn:name="carry_lookahead_adder_testbench.vhd"/>
<outfile xil_pn:name="carry_select_adder.vhd"/>
<outfile xil_pn:name="carry_select_adder_testbench.vhd"/>
<outfile xil_pn:name="full_adder.vhd"/>
<outfile xil_pn:name="half_adder.vhd"/>
<outfile xil_pn:name="mux_2to1.vhd"/>
<outfile xil_pn:name="not_gate.vhd"/>
<outfile xil_pn:name="or_gate.vhd"/>
<outfile xil_pn:name="ripple_adder.vhd"/>
<outfile xil_pn:name="ripple_adder_testbench.vhd"/>
<outfile xil_pn:name="xor_gate.vhd"/>
</transform>
<transform xil_pn:end_ts="1598533770" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-2550360960775524566" xil_pn:start_ts="1598533770">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598533770" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="6522114710509783112" xil_pn:start_ts="1598533770">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598533770" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-3119459493852624942" xil_pn:start_ts="1598533770">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform>
<transform xil_pn:end_ts="1598533770" xil_pn:in_ck="9127768792623154011" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1598533770">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="and_gate.vhd"/>
<outfile xil_pn:name="carry_calc.vhd"/>
<outfile xil_pn:name="carry_lookahead_adder.vhd"/>
<outfile xil_pn:name="carry_lookahead_adder_testbench.vhd"/>
<outfile xil_pn:name="carry_select_adder.vhd"/>
<outfile xil_pn:name="carry_select_adder_testbench.vhd"/>
<outfile xil_pn:name="full_adder.vhd"/>
<outfile xil_pn:name="half_adder.vhd"/>
<outfile xil_pn:name="mux_2to1.vhd"/>
<outfile xil_pn:name="not_gate.vhd"/>
<outfile xil_pn:name="or_gate.vhd"/>
<outfile xil_pn:name="ripple_adder.vhd"/>
<outfile xil_pn:name="ripple_adder_testbench.vhd"/>
<outfile xil_pn:name="xor_gate.vhd"/>
</transform>
<transform xil_pn:end_ts="1598533775" xil_pn:in_ck="9127768792623154011" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8031485519928181946" xil_pn:start_ts="1598533770">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="ripple_adder_testbench_beh.prj"/>
<outfile xil_pn:name="ripple_adder_testbench_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1598533775" xil_pn:in_ck="8685918471393109113" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-711152990239750339" xil_pn:start_ts="1598533775">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="ripple_adder_testbench_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1598534249" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1598534249">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598534249" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-5118038982566303674" xil_pn:start_ts="1598534249">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598534249" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="3421109988045354958" xil_pn:start_ts="1598534249">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598534249" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1598534249">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598534249" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="8819172970856571304" xil_pn:start_ts="1598534249">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598534249" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="3206529612922900429" xil_pn:start_ts="1598534249">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598534249" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="1232387714863853208" xil_pn:start_ts="1598534249">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598534263" xil_pn:in_ck="-5883998212107890467" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="-3725655605605876277" xil_pn:start_ts="1598534249">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="carry_lookahead_adder.lso"/>
<outfile xil_pn:name="carry_lookahead_adder.ngc"/>
<outfile xil_pn:name="carry_lookahead_adder.ngr"/>
<outfile xil_pn:name="carry_lookahead_adder.prj"/>
<outfile xil_pn:name="carry_lookahead_adder.stx"/>
<outfile xil_pn:name="carry_lookahead_adder.syr"/>
<outfile xil_pn:name="carry_lookahead_adder.xst"/>
<outfile xil_pn:name="carry_lookahead_adder_testbench_stx_beh.prj"/>
<outfile xil_pn:name="carry_lookahead_adder_xst.xrpt"/>
<outfile xil_pn:name="full_adder.ngr"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
</transforms>
</generated_project>