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MIPS

MIPS Processor Design for COEN6741

Do Not copy the code, drop this class ASAP.

Project Requirements

  • 32 bit pipelined MIPS
  • Implement 10 instructions: and sub xor andi subi add beq lw sw jr
  • Structural harzards free, data harzard and control harzard handled by stalling

Special thanks! Most of components originated from here

https://github.com/dugagjin/MIPS

Useful Repositories

https://github.com/PiJoules/MIPS-processor

https://github.com/cm4233/MIPS-Processor-VHDL/tree/master/VHDL%20Codes

https://github.com/BYVoid/MIPS32

Opcode References

https://opencores.org/projects/plasma/opcodes

Reference for ALUOp

http://fourier.eng.hmc.edu/e85_old/lectures/processor/node5.html

MIPS Conventional Registers Structure

http://www.cs.uwm.edu/classes/cs315/Bacon/Lecture/HTML/ch05s03.html

Convert Instructions to Hex format

http://www.kurtm.net/mipsasm/index.cgi