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DE2_i2sound.sta.rpt
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TimeQuest Timing Analyzer report for DE2_i2sound
Mon Jun 12 01:07:41 2023
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. SDC File List
5. Clocks
6. Slow Model Fmax Summary
7. Slow Model Setup Summary
8. Slow Model Hold Summary
9. Slow Model Recovery Summary
10. Slow Model Removal Summary
11. Slow Model Minimum Pulse Width Summary
12. Slow Model Minimum Pulse Width: '50MHZ'
13. Clock to Output Times
14. Minimum Clock to Output Times
15. Propagation Delay
16. Minimum Propagation Delay
17. Fast Model Setup Summary
18. Fast Model Hold Summary
19. Fast Model Recovery Summary
20. Fast Model Removal Summary
21. Fast Model Minimum Pulse Width Summary
22. Fast Model Minimum Pulse Width: '50MHZ'
23. Clock to Output Times
24. Minimum Clock to Output Times
25. Propagation Delay
26. Minimum Propagation Delay
27. Multicorner Timing Analysis Summary
28. Clock to Output Times
29. Minimum Clock to Output Times
30. Progagation Delay
31. Minimum Progagation Delay
32. Setup Transfers
33. Hold Transfers
34. Report TCCS
35. Report RSKM
36. Unconstrained Paths
37. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name ; DE2_i2sound ;
; Device Family ; Cyclone II ;
; Device Name ; EP2C35F672C6 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Unavailable ;
+--------------------+-------------------------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 16 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+-----------------------------------------------------+
; SDC File List ;
+-----------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ;
+-----------------+--------+--------------------------+
; DE2_i2sound.sdc ; OK ; Mon Jun 12 01:07:41 2023 ;
+-----------------+--------+--------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
; 50MHZ ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { 50MHZ } ;
+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
---------------------------
; Slow Model Fmax Summary ;
---------------------------
No paths to report.
----------------------------
; Slow Model Setup Summary ;
----------------------------
No paths to report.
---------------------------
; Slow Model Hold Summary ;
---------------------------
No paths to report.
-------------------------------
; Slow Model Recovery Summary ;
-------------------------------
No paths to report.
------------------------------
; Slow Model Removal Summary ;
------------------------------
No paths to report.
+----------------------------------------+
; Slow Model Minimum Pulse Width Summary ;
+-------+-------+------------------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+------------------------+
; 50MHZ ; 9.000 ; 0.000 ;
+-------+-------+------------------------+
+------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: '50MHZ' ;
+--------+--------------+----------------+------------------+-------+------------+---------------------------------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+------------------+-------+------------+---------------------------------+
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[0] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[0] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[10] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[10] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[1] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[1] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[2] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[2] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[3] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[3] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[4] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[4] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[5] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[5] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[6] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[6] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[7] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[7] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[8] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[8] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[9] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[9] ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; 50MHZ|combout ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; 50MHZ|combout ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; 50MHZ~clkctrl|inclk[0] ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; 50MHZ~clkctrl|inclk[0] ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; 50MHZ~clkctrl|outclk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; 50MHZ~clkctrl|outclk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[0]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[0]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[10]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[10]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[1]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[1]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[2]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[2]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[3]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[3]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[4]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[4]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[5]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[5]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[6]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[6]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[7]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[7]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[8]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[8]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[9]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[9]|clk ;
; 17.620 ; 20.000 ; 2.380 ; Port Rate ; 50MHZ ; Rise ; 50MHZ ;
+--------+--------------+----------------+------------------+-------+------------+---------------------------------+
+-----------------------------------------------------------------------+
; Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; AUD_XCK ; 50MHZ ; 7.649 ; 7.649 ; Rise ; 50MHZ ;
; I2C_SCLK ; 50MHZ ; 7.761 ; 7.761 ; Rise ; 50MHZ ;
+-----------+------------+-------+-------+------------+-----------------+
+-----------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; AUD_XCK ; 50MHZ ; 7.649 ; 7.649 ; Rise ; 50MHZ ;
; I2C_SCLK ; 50MHZ ; 7.761 ; 7.761 ; Rise ; 50MHZ ;
+-----------+------------+-------+-------+------------+-----------------+
+---------------------------------------------------------------+
; Propagation Delay ;
+-------------+-------------+--------+--------+--------+--------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+-------------+-------------+--------+--------+--------+--------+
; AUD_ADCDAT ; AUD_DACDAT ; 13.871 ; ; ; 13.871 ;
; AUD_ADCDAT ; gpio1_8 ; 10.471 ; ; ; 10.471 ;
; AUD_ADCLRCK ; gpio1_4 ; 10.389 ; ; ; 10.389 ;
; AUD_BCLK ; gpio1_2 ; 10.127 ; ; ; 10.127 ;
; SW17 ; AUD_DACDAT ; 13.408 ; 13.408 ; 13.408 ; 13.408 ;
; SW17 ; LEDR17 ; 9.611 ; ; ; 9.611 ;
+-------------+-------------+--------+--------+--------+--------+
+---------------------------------------------------------------+
; Minimum Propagation Delay ;
+-------------+-------------+--------+--------+--------+--------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+-------------+-------------+--------+--------+--------+--------+
; AUD_ADCDAT ; AUD_DACDAT ; 13.871 ; ; ; 13.871 ;
; AUD_ADCDAT ; gpio1_8 ; 10.471 ; ; ; 10.471 ;
; AUD_ADCLRCK ; gpio1_4 ; 10.389 ; ; ; 10.389 ;
; AUD_BCLK ; gpio1_2 ; 10.127 ; ; ; 10.127 ;
; SW17 ; AUD_DACDAT ; 13.408 ; 13.408 ; 13.408 ; 13.408 ;
; SW17 ; LEDR17 ; 9.611 ; ; ; 9.611 ;
+-------------+-------------+--------+--------+--------+--------+
----------------------------
; Fast Model Setup Summary ;
----------------------------
No paths to report.
---------------------------
; Fast Model Hold Summary ;
---------------------------
No paths to report.
-------------------------------
; Fast Model Recovery Summary ;
-------------------------------
No paths to report.
------------------------------
; Fast Model Removal Summary ;
------------------------------
No paths to report.
+----------------------------------------+
; Fast Model Minimum Pulse Width Summary ;
+-------+-------+------------------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+------------------------+
; 50MHZ ; 9.000 ; 0.000 ;
+-------+-------+------------------------+
+------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: '50MHZ' ;
+--------+--------------+----------------+------------------+-------+------------+---------------------------------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+------------------+-------+------------+---------------------------------+
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[0] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[0] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[10] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[10] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[1] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[1] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[2] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[2] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[3] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[3] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[4] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[4] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[5] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[5] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[6] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[6] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[7] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[7] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[8] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[8] ;
; 9.000 ; 10.000 ; 1.000 ; High Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[9] ;
; 9.000 ; 10.000 ; 1.000 ; Low Pulse Width ; 50MHZ ; Rise ; CLOCK_500:inst4|COUNTER_500[9] ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; 50MHZ|combout ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; 50MHZ|combout ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; 50MHZ~clkctrl|inclk[0] ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; 50MHZ~clkctrl|inclk[0] ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; 50MHZ~clkctrl|outclk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; 50MHZ~clkctrl|outclk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[0]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[0]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[10]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[10]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[1]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[1]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[2]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[2]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[3]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[3]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[4]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[4]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[5]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[5]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[6]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[6]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[7]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[7]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[8]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[8]|clk ;
; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[9]|clk ;
; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; 50MHZ ; Rise ; inst4|COUNTER_500[9]|clk ;
; 17.620 ; 20.000 ; 2.380 ; Port Rate ; 50MHZ ; Rise ; 50MHZ ;
+--------+--------------+----------------+------------------+-------+------------+---------------------------------+
+-----------------------------------------------------------------------+
; Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; AUD_XCK ; 50MHZ ; 4.298 ; 4.298 ; Rise ; 50MHZ ;
; I2C_SCLK ; 50MHZ ; 4.077 ; 4.077 ; Rise ; 50MHZ ;
+-----------+------------+-------+-------+------------+-----------------+
+-----------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; AUD_XCK ; 50MHZ ; 4.298 ; 4.298 ; Rise ; 50MHZ ;
; I2C_SCLK ; 50MHZ ; 4.077 ; 4.077 ; Rise ; 50MHZ ;
+-----------+------------+-------+-------+------------+-----------------+
+-----------------------------------------------------------+
; Propagation Delay ;
+-------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+-------------+-------------+-------+-------+-------+-------+
; AUD_ADCDAT ; AUD_DACDAT ; 7.618 ; ; ; 7.618 ;
; AUD_ADCDAT ; gpio1_8 ; 5.906 ; ; ; 5.906 ;
; AUD_ADCLRCK ; gpio1_4 ; 5.855 ; ; ; 5.855 ;
; AUD_BCLK ; gpio1_2 ; 5.722 ; ; ; 5.722 ;
; SW17 ; AUD_DACDAT ; 7.381 ; 7.381 ; 7.381 ; 7.381 ;
; SW17 ; LEDR17 ; 5.517 ; ; ; 5.517 ;
+-------------+-------------+-------+-------+-------+-------+
+-----------------------------------------------------------+
; Minimum Propagation Delay ;
+-------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+-------------+-------------+-------+-------+-------+-------+
; AUD_ADCDAT ; AUD_DACDAT ; 7.618 ; ; ; 7.618 ;
; AUD_ADCDAT ; gpio1_8 ; 5.906 ; ; ; 5.906 ;
; AUD_ADCLRCK ; gpio1_4 ; 5.855 ; ; ; 5.855 ;
; AUD_BCLK ; gpio1_2 ; 5.722 ; ; ; 5.722 ;
; SW17 ; AUD_DACDAT ; 7.381 ; 7.381 ; 7.381 ; 7.381 ;
; SW17 ; LEDR17 ; 5.517 ; ; ; 5.517 ;
+-------------+-------------+-------+-------+-------+-------+
+----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+------------------+-------+------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; 9.000 ;
; 50MHZ ; N/A ; N/A ; N/A ; N/A ; 9.000 ;
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
; 50MHZ ; N/A ; N/A ; N/A ; N/A ; 0.000 ;
+------------------+-------+------+----------+---------+---------------------+
+-----------------------------------------------------------------------+
; Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; AUD_XCK ; 50MHZ ; 7.649 ; 7.649 ; Rise ; 50MHZ ;
; I2C_SCLK ; 50MHZ ; 7.761 ; 7.761 ; Rise ; 50MHZ ;
+-----------+------------+-------+-------+------------+-----------------+
+-----------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; AUD_XCK ; 50MHZ ; 4.298 ; 4.298 ; Rise ; 50MHZ ;
; I2C_SCLK ; 50MHZ ; 4.077 ; 4.077 ; Rise ; 50MHZ ;
+-----------+------------+-------+-------+------------+-----------------+
+---------------------------------------------------------------+
; Progagation Delay ;
+-------------+-------------+--------+--------+--------+--------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+-------------+-------------+--------+--------+--------+--------+
; AUD_ADCDAT ; AUD_DACDAT ; 13.871 ; ; ; 13.871 ;
; AUD_ADCDAT ; gpio1_8 ; 10.471 ; ; ; 10.471 ;
; AUD_ADCLRCK ; gpio1_4 ; 10.389 ; ; ; 10.389 ;
; AUD_BCLK ; gpio1_2 ; 10.127 ; ; ; 10.127 ;
; SW17 ; AUD_DACDAT ; 13.408 ; 13.408 ; 13.408 ; 13.408 ;
; SW17 ; LEDR17 ; 9.611 ; ; ; 9.611 ;
+-------------+-------------+--------+--------+--------+--------+
+-----------------------------------------------------------+
; Minimum Progagation Delay ;
+-------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+-------------+-------------+-------+-------+-------+-------+
; AUD_ADCDAT ; AUD_DACDAT ; 7.618 ; ; ; 7.618 ;
; AUD_ADCDAT ; gpio1_8 ; 5.906 ; ; ; 5.906 ;
; AUD_ADCLRCK ; gpio1_4 ; 5.855 ; ; ; 5.855 ;
; AUD_BCLK ; gpio1_2 ; 5.722 ; ; ; 5.722 ;
; SW17 ; AUD_DACDAT ; 7.381 ; 7.381 ; 7.381 ; 7.381 ;
; SW17 ; LEDR17 ; 5.517 ; ; ; 5.517 ;
+-------------+-------------+-------+-------+-------+-------+
+---------------------------------------------------------------------+
; Setup Transfers ;
+------------+----------+------------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+------------+----------+----------+----------+
; 50MHZ ; 50MHZ ; false path ; 0 ; 0 ; 0 ;
+------------+----------+------------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+---------------------------------------------------------------------+
; Hold Transfers ;
+------------+----------+------------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+------------+----------+----------+----------+
; 50MHZ ; 50MHZ ; false path ; 0 ; 0 ; 0 ;
+------------+----------+------------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 5 ; 5 ;
; Unconstrained Input Ports ; 22 ; 22 ;
; Unconstrained Input Port Paths ; 1604 ; 1604 ;
; Unconstrained Output Ports ; 62 ; 62 ;
; Unconstrained Output Port Paths ; 87 ; 87 ;
+---------------------------------+-------+------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Mon Jun 12 01:07:40 2023
Info: Command: quartus_sta DE2_i2sound -c DE2_i2sound
Info: qsta_default_script.tcl version: #1
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'DE2_i2sound.sdc'
Warning (332060): Node: CLOCK_500:inst4|COUNTER_500[9] was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: i2c:inst|END was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: AUD_BCLK was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: keytr:inst1|KEYON was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY1 was determined to be a clock but was found without an associated clock assignment.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow Model
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 9.000
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 9.000 0.000 50MHZ
Info (332001): The selected device family is not supported by the report_metastability command.
Info: Analyzing Fast Model
Warning (332060): Node: CLOCK_500:inst4|COUNTER_500[9] was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: i2c:inst|END was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: AUD_BCLK was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: keytr:inst1|KEYON was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY1 was determined to be a clock but was found without an associated clock assignment.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 9.000
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 9.000 0.000 50MHZ
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 10 warnings
Info: Peak virtual memory: 4581 megabytes
Info: Processing ended: Mon Jun 12 01:07:41 2023
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01