winch(aarch64): Improve 32-bit {s,u}div

[saulecabrera]

While reviewing #9762, I realized that in the case of 32-bit operands a sign-extension is required given that cranelift-codegen, only accepts 64-bit operands.

The ARM64 documentation states 1, 2 that 32-bit operands for division are allowed.

Introducing support for 32-bit operands means that in Winch we can skip the extension sequence when dealing with 32-bit operands.

As a side note, it seems that when migrating to ISLE the intention was to add support for 32-bit operands.

cc @alexcrichton / @cfallin I'm not entirely familiar with the development history of the Aarch64 backend, is there any other reason to be aware of when considering support for 32-bit operands?

[cfallin]

I'm not aware of any reasons why we couldn't add 32-bit variants of the div instruction family; going all the way back to the original PR for the aarch64 backend it looks like I had only implemented SDiv64 and UDiv64 and added the extensions. Probably this is a case of "no one has had occasion to add it yet"...

(Incidentally, x86-64 has 32-bit divides too; and on both architectures I'd expect that high-performance implementations would probably take ~half the latency for a 32-bit version; so not a small win for any benchmark with a divide in a critical path.)

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[MarinPostma]

I'd like to take a stab at that after I'm done with winch. Any guidance on how I should tackle that?

[saulecabrera]

One approach could be to take a look at how similar instructions have been added in the past e.g., #8453