diff --git a/Dockerfile b/Dockerfile index 3ad51b7015..32d92ce264 100644 --- a/Dockerfile +++ b/Dockerfile @@ -53,8 +53,8 @@ RUN python3 setup.py bdist_wheel && python3 -m pip install dist/tvm-*.whl WORKDIR /home RUN git clone https://github.com/cucapra/dahlia.git WORKDIR /home/dahlia -## Checkout specific version. Fetch before checkout because clone might be cached. -RUN git fetch --all && git checkout 88e05e5 +## Checkout specific version +RUN git checkout 51954e7 RUN sbt "; getHeaders; assembly" # Add the Calyx source code from the build context diff --git a/calyx-ir/src/common.rs b/calyx-ir/src/common.rs index 4e5a7a25be..139c16e70d 100644 --- a/calyx-ir/src/common.rs +++ b/calyx-ir/src/common.rs @@ -32,9 +32,9 @@ impl WRC { pub fn upgrade(&self) -> RRC { let Some(r) = self.internal.upgrade() else { #[cfg(debug_assertions)] - unreachable!("weak reference points to a dropped value. Original object's name: `{}'", self.debug_name); + unreachable!("weak reference points to a dropped. Original object's name: `{}'", self.debug_name); #[cfg(not(debug_assertions))] - unreachable!("weak reference points to a dropped value."); + unreachable!("weak reference points to a dropped."); }; r } diff --git a/calyx-ir/src/component.rs b/calyx-ir/src/component.rs index f9752afd15..b0923f5fcf 100644 --- a/calyx-ir/src/component.rs +++ b/calyx-ir/src/component.rs @@ -231,14 +231,6 @@ impl Component { self.namegen.gen_name(prefix) } - /// Check whether this component is purely structural, i.e. has no groups or control - pub fn is_structural(&self) -> bool { - self.groups.is_empty() - && self.comb_groups.is_empty() - && self.static_groups.is_empty() - && self.control.borrow().is_empty() - } - /// Check whether this is a static component. /// A static component is a component which has a latency field. pub fn is_static(&self) -> bool { @@ -324,7 +316,7 @@ impl Component { #[derive(Debug)] pub struct IdList(LinkedHashMap>); -/// Simple iter impl delegating to the [`Values`](linked_hash_map::Values). +/// Simple into-iter impl delegating to the [`Values`](linked_hash_map::Values). impl<'a, T: GetName> IntoIterator for &'a IdList { type Item = &'a RRC; diff --git a/calyx-opt/src/default_passes.rs b/calyx-opt/src/default_passes.rs index 2d5c2bd2c0..74782acb50 100644 --- a/calyx-opt/src/default_passes.rs +++ b/calyx-opt/src/default_passes.rs @@ -3,9 +3,9 @@ use crate::passes::{ AddGuard, Canonicalize, CellShare, ClkInsertion, CollapseControl, CombProp, CompileInvoke, CompileRepeat, CompileStatic, CompileStaticInterface, CompileSync, CompileSyncWithoutSyncReg, ComponentInliner, DataPathInfer, - DeadAssignmentRemoval, DeadCellRemoval, DeadGroupRemoval, DefaultAssigns, - DiscoverExternal, Externalize, GoInsertion, GroupToInvoke, GroupToSeq, - HoleInliner, InferShare, LowerGuards, MergeAssign, Papercut, ParToSeq, + DeadAssignmentRemoval, DeadCellRemoval, DeadGroupRemoval, DiscoverExternal, + Externalize, GoInsertion, GroupToInvoke, GroupToSeq, HoleInliner, + InferShare, LowerGuards, MergeAssign, Papercut, ParToSeq, RegisterUnsharing, RemoveIds, ResetInsertion, SimplifyStaticGuards, SimplifyWithControl, StaticInference, StaticInliner, StaticPromotion, SynthesisPapercut, TopDownCompileControl, UnrollBounded, WellFormed, @@ -59,7 +59,6 @@ impl PassManager { pm.register_pass::()?; pm.register_pass::()?; pm.register_pass::()?; - pm.register_pass::()?; // Enabled in the synthesis compilation flow pm.register_pass::()?; @@ -135,7 +134,6 @@ impl PassManager { ClkInsertion, ResetInsertion, MergeAssign, - DefaultAssigns, ] ); diff --git a/calyx-opt/src/passes/default_assigns.rs b/calyx-opt/src/passes/default_assigns.rs deleted file mode 100644 index 7f1e3cb53d..0000000000 --- a/calyx-opt/src/passes/default_assigns.rs +++ /dev/null @@ -1,129 +0,0 @@ -use crate::analysis::AssignmentAnalysis; -use crate::traversal::{Action, ConstructVisitor, Named, VisResult, Visitor}; -use calyx_ir::{self as ir, LibrarySignatures}; -use calyx_utils::{CalyxResult, Error}; -use itertools::Itertools; -use std::collections::HashMap; - -/// Adds default assignments to all non-`@data` ports of an instance. -pub struct DefaultAssigns { - /// Mapping from component to data ports - data_ports: HashMap>, -} - -impl Named for DefaultAssigns { - fn name() -> &'static str { - "default-assigns" - } - - fn description() -> &'static str { - "adds default assignments to all non-`@data` ports of an instance." - } -} - -impl ConstructVisitor for DefaultAssigns { - fn from(ctx: &ir::Context) -> CalyxResult - where - Self: Sized, - { - let data_ports = ctx - .lib - .signatures() - .map(|sig| { - let ports = sig.signature.iter().filter_map(|p| { - if p.direction == ir::Direction::Input - && !p.attributes.has(ir::BoolAttr::Data) - && !p.attributes.has(ir::BoolAttr::Clk) - && !p.attributes.has(ir::BoolAttr::Reset) - { - Some(p.name()) - } else { - None - } - }); - (sig.name, ports.collect()) - }) - .collect(); - Ok(Self { data_ports }) - } - - fn clear_data(&mut self) { - /* shared across components */ - } -} - -impl Visitor for DefaultAssigns { - fn start( - &mut self, - comp: &mut ir::Component, - sigs: &LibrarySignatures, - _comps: &[ir::Component], - ) -> VisResult { - if !comp.is_structural() { - return Err(Error::pass_assumption( - Self::name(), - format!("component {} is not purely structural", comp.name), - )); - } - - // We only need to consider write set of the continuous assignments - let writes = comp - .continuous_assignments - .iter() - .analysis() - .writes() - .group_by_cell(); - - let mut assigns = Vec::new(); - - let mt = vec![]; - let cells = comp.cells.iter().cloned().collect_vec(); - let mut builder = ir::Builder::new(comp, sigs); - - for cr in &cells { - let cell = cr.borrow(); - let Some(typ) = cell.type_name() else { - continue; - }; - let Some(required) = self.data_ports.get(&typ) else { - continue; - }; - - // For all the assignments not in the write set, add a default assignment - let cell_writes = writes - .get(&cell.name()) - .unwrap_or(&mt) - .iter() - .map(|p| { - let p = p.borrow(); - p.name - }) - .collect_vec(); - - assigns.extend( - required.iter().filter(|p| !cell_writes.contains(p)).map( - |name| { - let port = cell.get(name); - let zero = builder.add_constant(0, port.borrow().width); - let assign: ir::Assignment = builder - .build_assignment( - cell.get(name), - zero.borrow().get("out"), - ir::Guard::True, - ); - log::info!( - "Adding {}", - ir::Printer::assignment_to_str(&assign) - ); - assign - }, - ), - ); - } - - comp.continuous_assignments.extend(assigns); - - // Purely structural pass - Ok(Action::Stop) - } -} diff --git a/calyx-opt/src/passes/mod.rs b/calyx-opt/src/passes/mod.rs index 6cb73f2c7f..87e9c81718 100644 --- a/calyx-opt/src/passes/mod.rs +++ b/calyx-opt/src/passes/mod.rs @@ -35,7 +35,6 @@ mod sync; mod add_guard; mod compile_static_interface; mod data_path_infer; -mod default_assigns; mod discover_external; mod simplify_with_control; mod synthesis_papercut; @@ -82,7 +81,6 @@ pub use sync::CompileSyncWithoutSyncReg; // pub use simplify_guards::SimplifyGuards; pub use add_guard::AddGuard; pub use compile_static_interface::CompileStaticInterface; -pub use default_assigns::DefaultAssigns; pub use synthesis_papercut::SynthesisPapercut; pub use top_down_compile_control::TopDownCompileControl; pub use unroll_bound::UnrollBounded; diff --git a/calyx-opt/src/passes/papercut.rs b/calyx-opt/src/passes/papercut.rs index 72b26dd947..aa98626ed5 100644 --- a/calyx-opt/src/passes/papercut.rs +++ b/calyx-opt/src/passes/papercut.rs @@ -28,30 +28,6 @@ pub struct Papercut { cont_cells: HashSet, } -impl Papercut { - #[allow(unused)] - /// String representation of the write together and read together specifications. - /// Used for debugging. Should not be relied upon by external users. - fn fmt_write_together_spec(&self) -> String { - self.write_together - .iter() - .map(|(prim, writes)| { - let writes = writes - .iter() - .map(|write| { - write - .iter() - .sorted() - .map(|port| format!("{port}")) - .join(", ") - }) - .join("; "); - format!("{}: [{}]", prim, writes) - }) - .join("\n") - } -} - impl ConstructVisitor for Papercut { fn from(ctx: &ir::Context) -> CalyxResult { let write_together = @@ -256,7 +232,7 @@ impl Papercut { .join(", "); let msg = format!("Required signal not driven inside the group.\ - \nWhen reading the port `{}.{}', the ports [{}] must be written to.\ + \nWhen read the port `{}.{}', the ports [{}] must be written to.\ \nThe primitive type `{}' requires this invariant.", inst, read, @@ -269,35 +245,30 @@ impl Papercut { } for ((inst, comp_type), writes) in all_writes { if let Some(spec) = self.write_together.get(&comp_type) { - // For each write together spec. for required in spec { // It should either be the case that: // 1. `writes` contains no writes that overlap with `required` // In which case `required - writes` == `required`. // 2. `writes` contains writes that overlap with `required` // In which case `required - writes == {}` - let mut diff: HashSet<_> = - required.difference(&writes).copied().collect(); - if diff.is_empty() || diff == *required { - continue; + let mut diff = required - &writes; + if !diff.is_empty() && diff != *required { + let first = writes.iter().sorted().next().unwrap(); + let missing = diff + .drain() + .sorted() + .map(|port| format!("{}.{}", inst, port)) + .join(", "); + let msg = + format!("Required signal not driven inside the group.\ + \nWhen writing to the port `{}.{}', the ports [{}] must also be written to.\ + \nThe primitive type `{}' requires this invariant.", + inst, + first, + missing, + comp_type); + return Err(Error::papercut(msg)); } - - let first = - writes.intersection(required).sorted().next().unwrap(); - let missing = diff - .drain() - .sorted() - .map(|port| format!("{}.{}", inst, port)) - .join(", "); - let msg = - format!("Required signal not driven inside the group. \ - When writing to the port `{}.{}', the ports [{}] must also be written to. \ - The primitive type `{}' specifies this using a @write_together spec.", - inst, - first, - missing, - comp_type); - return Err(Error::papercut(msg)); } } } diff --git a/calyx-py/calyx/builder.py b/calyx-py/calyx/builder.py index d14aea5543..159e3ce686 100644 --- a/calyx-py/calyx/builder.py +++ b/calyx-py/calyx/builder.py @@ -605,8 +605,8 @@ def mem_read_seq_d1(self, mem, i, groupname=None): groupname = groupname or f"read_from_{mem.name()}" with self.group(groupname) as read_grp: mem.addr0 = i - mem.content_en = 1 - read_grp.done = mem.done + mem.read_en = 1 + read_grp.done = mem.read_done return read_grp def mem_write_seq_d1_to_reg(self, mem, reg, groupname=None): @@ -631,8 +631,7 @@ def mem_store_seq_d1(self, mem, i, val, groupname=None): mem.addr0 = i mem.write_en = 1 mem.write_data = val - mem.content_en = 1 - store_grp.done = mem.done + store_grp.done = mem.write_done return store_grp def mem_load_to_mem(self, mem, i, ans, j, groupname=None): @@ -1100,7 +1099,7 @@ def infer_width(self, port_name) -> int: return inst.args[2] if port_name == "in": return inst.args[0] - if prim == "seq_mem_d1" and port_name == "content_en": + if prim == "seq_mem_d1" and port_name == "read_en": return 1 if prim in ( "std_mult_pipe", diff --git a/examples/futil/dot-product.expect b/examples/futil/dot-product.expect index dd5edecb83..892882468c 100644 --- a/examples/futil/dot-product.expect +++ b/examples/futil/dot-product.expect @@ -115,8 +115,6 @@ component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) { A_read0_0.reset = reset; A_read0_0.in = fsm.out == 4'd0 & early_reset_static_seq_go.out ? A0.read_data; A_read0_0.in = fsm.out == 4'd4 & early_reset_static_seq_go.out ? mult_pipe0.out; - A0.write_en = 1'd0; - B0.write_en = 1'd0; } control {} } diff --git a/examples/futil/vectorized-add.expect b/examples/futil/vectorized-add.expect index 52171e14b4..45a34acfd1 100644 --- a/examples/futil/vectorized-add.expect +++ b/examples/futil/vectorized-add.expect @@ -105,8 +105,6 @@ component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) { A_read0_0.clk = clk; A_read0_0.reset = reset; A_read0_0.in = fsm.out == 3'd0 & early_reset_static_seq_go.out ? A0.read_data; - A0.write_en = 1'd0; - B0.write_en = 1'd0; } control {} } diff --git a/interp/src/primitives/stateful/memories.rs b/interp/src/primitives/stateful/memories.rs index a2a3b1486d..01b47e9573 100644 --- a/interp/src/primitives/stateful/memories.rs +++ b/interp/src/primitives/stateful/memories.rs @@ -446,6 +446,7 @@ enum SeqMemAction { Read(T), Write(T, Value), Reset, + Error, } impl Default for SeqMemAction { @@ -555,10 +556,10 @@ impl Primitive for SeqMem { fn validate(&self, inputs: &[(ir::Id, &Value)]) { validate![inputs; - content_en: 1, + read_en: 1, write_en: 1, reset: 1, - write_data: self.width + r#in: self.width ]; self.mem_binder.validate(inputs); } @@ -568,7 +569,7 @@ impl Primitive for SeqMem { inputs: &[(ir::Id, &Value)], ) -> InterpreterResult> { get_inputs![inputs; - content_en [bool]: "content_en", + read_en [bool]: "read_en", write_en [bool]: "write_en", reset [bool]: "reset", input: "write_data" @@ -580,9 +581,11 @@ impl Primitive for SeqMem { self.update = if reset { SeqMemAction::Reset - } else if write_en && content_en { + } else if write_en && read_en { + SeqMemAction::Error + } else if write_en { SeqMemAction::Write(idx, input.clone()) - } else if content_en { + } else if read_en { SeqMemAction::Read(idx) } else { SeqMemAction::None @@ -604,7 +607,8 @@ impl Primitive for SeqMem { Ok(vec![ ("read_data".into(), self.read_out.clone()), - ("done".into(), Value::bit_high()), + ("read_done".into(), Value::bit_high()), + ("write_done".into(), Value::bit_low()), ]) } SeqMemAction::Write(idx, v) => { @@ -617,20 +621,24 @@ impl Primitive for SeqMem { Ok(vec![ ("read_data".into(), self.read_out.clone()), - ("done".into(), Value::bit_high()), + ("read_done".into(), Value::bit_low()), + ("write_done".into(), Value::bit_high()), ]) } SeqMemAction::Reset => { self.read_out = Value::zeroes(self.width); Ok(vec![ ("read_data".into(), self.read_out.clone()), - ("done".into(), Value::bit_low()), + ("read_done".into(), Value::bit_low()), + ("write_done".into(), Value::bit_low()), ]) } SeqMemAction::None => Ok(vec![ ("read_data".into(), self.read_out.clone()), - ("done".into(), Value::bit_low()), + ("read_done".into(), Value::bit_low()), + ("write_done".into(), Value::bit_low()), ]), + SeqMemAction::Error => Err(InterpreterError::SeqMemoryError.into()), } } @@ -642,7 +650,8 @@ impl Primitive for SeqMem { Ok(vec![ ("read_data".into(), self.read_out.clone()), - ("done".into(), Value::bit_low()), + ("read_done".into(), Value::bit_low()), + ("write_done".into(), Value::bit_low()), ]) } diff --git a/primitives/memories/seq.futil b/primitives/memories/seq.futil index 57517f882f..89d163d3a7 100644 --- a/primitives/memories/seq.futil +++ b/primitives/memories/seq.futil @@ -3,58 +3,66 @@ extern "seq.sv" { primitive seq_mem_d1[WIDTH, SIZE, IDX_SIZE]( @clk clk: 1, @reset reset: 1, - @write_together(1) @data addr0: IDX_SIZE, - @write_together(1) @interval(1) @go(1) content_en: 1, + @data addr0: IDX_SIZE, // Write ports - @write_together(2) write_en: 1, - @write_together(2) @data write_data: WIDTH + @write_together(1) @interval(1) @go(1) write_en: 1, + @write_together(1) @data write_data: WIDTH, + // Read ports + @interval(1) @go(2) read_en: 1 ) -> ( @stable read_data: WIDTH, - @done(1) done: 1 + @done(1) write_done: 1, + @done(2) read_done: 1 ); primitive seq_mem_d2[WIDTH, D0_SIZE, D1_SIZE, D0_IDX_SIZE, D1_IDX_SIZE]( @clk clk: 1, @reset reset: 1, - @write_together(1) @data addr0: D0_IDX_SIZE, - @write_together(1) @data addr1: D1_IDX_SIZE, - @write_together(1) @interval(1) @go(1) content_en: 1, + @data addr0: D0_IDX_SIZE, + @data addr1: D1_IDX_SIZE, // Write ports - @write_together(2) write_en: 1, - @write_together(2) @data write_data: WIDTH + @write_together(1) @interval(1) @go(1) write_en: 1, + @write_together(1) @data write_data: WIDTH, + // Read ports + @interval(1) @go(2) read_en: 1 ) -> ( @stable read_data: WIDTH, - @done(1) done: 1 + @done(1) write_done: 1, + @done(2) read_done: 1 ); primitive seq_mem_d3[WIDTH, D0_SIZE, D1_SIZE, D2_SIZE, D0_IDX_SIZE, D1_IDX_SIZE, D2_IDX_SIZE]( @clk clk: 1, @reset reset: 1, - @write_together(1) @data addr0: D0_IDX_SIZE, - @write_together(1) @data addr1: D1_IDX_SIZE, - @write_together(1) @data addr2: D2_IDX_SIZE, - @write_together(1) @interval(1) @go(1) content_en: 1, + @data addr0: D0_IDX_SIZE, + @data addr1: D1_IDX_SIZE, + @data addr2: D2_IDX_SIZE, // Write ports - @write_together(2) write_en: 1, - @write_together(2) @data write_data: WIDTH + @write_together(1) @interval(1) @go(1) write_en: 1, + @write_together(1) @data write_data: WIDTH, + // Read ports + @interval(1) @go(2) read_en: 1 ) -> ( @stable read_data: WIDTH, - @done(1) done: 1 + @done(1) write_done: 1, + @done(2) read_done: 1 ); primitive seq_mem_d4[WIDTH, D0_SIZE, D1_SIZE, D2_SIZE, D3_SIZE, D0_IDX_SIZE, D1_IDX_SIZE, D2_IDX_SIZE, D3_IDX_SIZE]( @clk clk: 1, @reset reset: 1, - @write_together(1) @data addr0: D0_IDX_SIZE, - @write_together(1) @data addr1: D1_IDX_SIZE, - @write_together(1) @data addr2: D2_IDX_SIZE, - @write_together(1) @data addr3: D3_IDX_SIZE, - @write_together(1) @interval(1) @go(1) content_en: 1, + @data addr0: D0_IDX_SIZE, + @data addr1: D1_IDX_SIZE, + @data addr2: D2_IDX_SIZE, + @data addr3: D3_IDX_SIZE, // Write ports - @write_together(2) write_en: 1, - @write_together(2) @data write_data: WIDTH + @write_together(1) @interval(1) @go(1) write_en: 1, + @write_together(1) @data write_data: WIDTH, + // Read ports + @interval(1) @go(2) read_en: 1 ) -> ( @stable read_data: WIDTH, - @done(1) done: 1 + @done(1) write_done: 1, + @done(2) read_done: 1 ); -} +} \ No newline at end of file diff --git a/primitives/memories/seq.sv b/primitives/memories/seq.sv index 68712f2391..4b90c1b946 100644 --- a/primitives/memories/seq.sv +++ b/primitives/memories/seq.sv @@ -14,18 +14,19 @@ module seq_mem_d1 #( input wire logic clk, input wire logic reset, input wire logic [IDX_SIZE-1:0] addr0, - input wire logic content_en, - output logic done, // Read signal + input wire logic read_en, output logic [ WIDTH-1:0] read_data, + output logic read_done, // Write signals input wire logic [ WIDTH-1:0] write_data, - input wire logic write_en + input wire logic write_en, + output logic write_done ); // Internal memory - logic [WIDTH-1:0] mem[SIZE-1:0]; + (* ram_style = "ultra" *) logic [WIDTH-1:0] mem[SIZE-1:0]; // Register for the read output logic [WIDTH-1:0] read_out; @@ -35,10 +36,10 @@ module seq_mem_d1 #( always_ff @(posedge clk) begin if (reset) begin read_out <= '0; - end else if (content_en && !write_en) begin + end else if (read_en) begin /* verilator lint_off WIDTH */ read_out <= mem[addr0]; - end else if (content_en && write_en) begin + end else if (write_en) begin // Explicitly clobber the read output when a write is performed read_out <= 'x; end else begin @@ -46,27 +47,38 @@ module seq_mem_d1 #( end end - // Propagate the done signal + // Propagate the read_done signal always_ff @(posedge clk) begin if (reset) begin - done <= '0; - end else if (content_en) begin - done <= '1; + read_done <= '0; + end else if (read_en) begin + read_done <= '1; end else begin - done <= '0; + read_done <= '0; end end // Write value to the memory always_ff @(posedge clk) begin - if (!reset && content_en && write_en) + if (!reset && write_en) mem[addr0] <= write_data; end + // Propagate the write_done signal + always_ff @(posedge clk) begin + if (reset) begin + write_done <= '0; + end else if (write_en) begin + write_done <= 1'd1; + end else begin + write_done <= '0; + end + end + // Check for out of bounds access `ifdef VERILATOR always_comb begin - if (content_en && !write_en) + if (read_en) if (addr0 >= SIZE) $error( "comb_mem_d1: Out of bounds access\n", @@ -74,6 +86,10 @@ module seq_mem_d1 #( "SIZE: %0d", SIZE ); end + always_comb begin + if (read_en && write_en) + $error("Simultaneous read and write attempted\n"); + end `endif endmodule @@ -89,23 +105,24 @@ module seq_mem_d2 #( input wire logic reset, input wire logic [D0_IDX_SIZE-1:0] addr0, input wire logic [D1_IDX_SIZE-1:0] addr1, - input wire logic content_en, - output logic done, // Read signal + input wire logic read_en, output logic [WIDTH-1:0] read_data, + output logic read_done, // Write signals input wire logic write_en, - input wire logic [ WIDTH-1:0] write_data + input wire logic [ WIDTH-1:0] write_data, + output logic write_done ); wire [D0_IDX_SIZE+D1_IDX_SIZE-1:0] addr; assign addr = addr0 * D1_SIZE + addr1; seq_mem_d1 #(.WIDTH(WIDTH), .SIZE(D0_SIZE * D1_SIZE), .IDX_SIZE(D0_IDX_SIZE+D1_IDX_SIZE)) mem (.clk(clk), .reset(reset), .addr0(addr), - .content_en(content_en), .read_data(read_data), .write_data(write_data), .write_en(write_en), - .done(done)); + .read_en(read_en), .read_data(read_data), .read_done(read_done), .write_data(write_data), .write_en(write_en), + .write_done(write_done)); endmodule module seq_mem_d3 #( @@ -123,23 +140,24 @@ module seq_mem_d3 #( input wire logic [D0_IDX_SIZE-1:0] addr0, input wire logic [D1_IDX_SIZE-1:0] addr1, input wire logic [D2_IDX_SIZE-1:0] addr2, - input wire logic content_en, - output logic done, // Read signal + input wire logic read_en, output logic [WIDTH-1:0] read_data, + output logic read_done, // Write signals input wire logic write_en, - input wire logic [ WIDTH-1:0] write_data + input wire logic [ WIDTH-1:0] write_data, + output logic write_done ); wire [D0_IDX_SIZE+D1_IDX_SIZE+D2_IDX_SIZE-1:0] addr; assign addr = addr0 * (D1_SIZE * D2_SIZE) + addr1 * (D2_SIZE) + addr2; seq_mem_d1 #(.WIDTH(WIDTH), .SIZE(D0_SIZE * D1_SIZE * D2_SIZE), .IDX_SIZE(D0_IDX_SIZE+D1_IDX_SIZE+D2_IDX_SIZE)) mem (.clk(clk), .reset(reset), .addr0(addr), - .content_en(content_en), .read_data(read_data), .write_data(write_data), .write_en(write_en), - .done(done)); + .read_en(read_en), .read_data(read_data), .read_done(read_done), .write_data(write_data), .write_en(write_en), + .write_done(write_done)); endmodule module seq_mem_d4 #( @@ -160,21 +178,22 @@ module seq_mem_d4 #( input wire logic [D1_IDX_SIZE-1:0] addr1, input wire logic [D2_IDX_SIZE-1:0] addr2, input wire logic [D3_IDX_SIZE-1:0] addr3, - input wire logic content_en, - output logic done, // Read signal + input wire logic read_en, output logic [WIDTH-1:0] read_data, + output logic read_done, // Write signals input wire logic write_en, - input wire logic [ WIDTH-1:0] write_data + input wire logic [ WIDTH-1:0] write_data, + output logic write_done ); wire [D0_IDX_SIZE+D1_IDX_SIZE+D2_IDX_SIZE+D3_IDX_SIZE-1:0] addr; assign addr = addr0 * (D1_SIZE * D2_SIZE * D3_SIZE) + addr1 * (D2_SIZE * D3_SIZE) + addr2 * (D3_SIZE) + addr3; seq_mem_d1 #(.WIDTH(WIDTH), .SIZE(D0_SIZE * D1_SIZE * D2_SIZE * D3_SIZE), .IDX_SIZE(D0_IDX_SIZE+D1_IDX_SIZE+D2_IDX_SIZE+D3_IDX_SIZE)) mem (.clk(clk), .reset(reset), .addr0(addr), - .content_en(content_en), .read_data(read_data), .write_data(write_data), .write_en(write_en), - .done(done)); -endmodule + .read_en(read_en), .read_data(read_data), .read_done(read_done), .write_data(write_data), .write_en(write_en), + .write_done(write_done)); +endmodule \ No newline at end of file diff --git a/tests/backend/verilog/memory-with-external-attribute.expect b/tests/backend/verilog/memory-with-external-attribute.expect index e6e7ee1639..4c08fe3ba9 100644 --- a/tests/backend/verilog/memory-with-external-attribute.expect +++ b/tests/backend/verilog/memory-with-external-attribute.expect @@ -595,14 +595,10 @@ comb_mem_d1 # ( .write_en(m1_write_en) ); wire _guard0 = 1; -assign m1_write_en = 1'd0; assign m1_clk = clk; -assign m1_addr0 = 4'd0; assign m1_reset = reset; assign done = m1_done; -assign m0_write_en = 1'd0; assign m0_clk = clk; -assign m0_addr0 = 4'd0; assign m0_reset = reset; // COMPONENT END: main endmodule diff --git a/tests/backend/yxi/seq-mem-d4-add.futil b/tests/backend/yxi/seq-mem-d4-add.futil index 59dfdbb467..5e09f5f067 100644 --- a/tests/backend/yxi/seq-mem-d4-add.futil +++ b/tests/backend/yxi/seq-mem-d4-add.futil @@ -76,8 +76,8 @@ component main() -> () { in1.addr1 = j.out; in1.addr2 = k.out; in1.addr3 = l.out; - in1.content_en = 1'd1; - in1_reg.write_en = in1.done; + in1.read_en = 1'd1; + in1_reg.write_en = in1.read_done; in1_reg.in = in1.read_data; read_in1[done] = in1_reg.done; } @@ -86,8 +86,8 @@ component main() -> () { in2.addr1 = j.out; in2.addr2 = k.out; in2.addr3 = l.out; - in2.content_en = 1'd1; - in2_reg.write_en = in2.done; + in2.read_en = 1'd1; + in2_reg.write_en = in2.read_done; in2_reg.in = in2.read_data; read_in2[done] = in2_reg.done; } @@ -98,10 +98,9 @@ component main() -> () { out.addr1 = j.out; out.addr2 = k.out; out.addr3 = l.out; - out.content_en = 1'd1; out.write_en = 1'd1; out.write_data = add.out; - update_val[done] = out.done; + update_val[done] = out.write_done; } group incr_i { add_i.left = i.out; diff --git a/tests/correctness/ref-cells/higher-order.futil b/tests/correctness/ref-cells/higher-order.futil index 77d517a2ba..a3038600be 100644 --- a/tests/correctness/ref-cells/higher-order.futil +++ b/tests/correctness/ref-cells/higher-order.futil @@ -69,9 +69,9 @@ component map_f() -> () { incr[done] = idx.done; } group read_in { - in.content_en = 1'd1; + in.read_en = 1'd1; in.addr0 = idx.out; - read_in[done] = in.done; + read_in[done] = in.read_done; } group write_r { r.write_en = 1'd1; @@ -79,11 +79,10 @@ component map_f() -> () { write_r[done] = r.done; } group write_out { - out.content_en = 1'd1; out.write_en = 1'd1; out.addr0 = idx.out; out.write_data = r.out; - write_out[done] = out.done; + write_out[done] = out.write_done; } } control { @@ -112,17 +111,15 @@ component main() -> () { wires { group f1_stats { stats.addr0 = 2'd0; - stats.content_en = 1'd1; stats.write_data = f1.processed; stats.write_en = 1'd1; - f1_stats[done] = stats.done; + f1_stats[done] = stats.write_done; } group f2_stats { stats.addr0 = 2'd1; - stats.content_en = 1'd1; stats.write_data = f2.processed; stats.write_en = 1'd1; - f2_stats[done] = stats.done; + f2_stats[done] = stats.write_done; } } control { diff --git a/tests/correctness/seq-mem-d4-add.futil b/tests/correctness/seq-mem-d4-add.futil index 1a8a4c6f37..31abdcbcd3 100644 --- a/tests/correctness/seq-mem-d4-add.futil +++ b/tests/correctness/seq-mem-d4-add.futil @@ -70,23 +70,23 @@ component main() -> () { lt4.left = l.out; lt4.right = 3'd4; } - group read_in1 { + group read_in1{ in1.addr0 = i.out; in1.addr1 = j.out; in1.addr2 = k.out; in1.addr3 = l.out; - in1.content_en = 1'd1; - in1_reg.write_en = in1.done; + in1.read_en = 1'd1; + in1_reg.write_en = in1.read_done; in1_reg.in = in1.read_data; read_in1[done] = in1_reg.done; } - group read_in2 { + group read_in2{ in2.addr0 = i.out; in2.addr1 = j.out; in2.addr2 = k.out; in2.addr3 = l.out; - in2.content_en = 1'd1; - in2_reg.write_en = in2.done; + in2.read_en = 1'd1; + in2_reg.write_en = in2.read_done; in2_reg.in = in2.read_data; read_in2[done] = in2_reg.done; } @@ -97,10 +97,9 @@ component main() -> () { out.addr1 = j.out; out.addr2 = k.out; out.addr3 = l.out; - out.content_en = 1'd1; out.write_en = 1'd1; out.write_data = add.out; - update_val[done] = out.done; + update_val[done] = out.write_done; } group incr_i { add_i.left = i.out; diff --git a/tests/correctness/seq-mem-dot-product.futil b/tests/correctness/seq-mem-dot-product.futil index 856353f671..09f0425597 100644 --- a/tests/correctness/seq-mem-dot-product.futil +++ b/tests/correctness/seq-mem-dot-product.futil @@ -39,14 +39,14 @@ component main() -> () { // Prime memories for reading group prime_in1 { - in1.content_en = 1'd1; + in1.read_en = 1'd1; in1.addr0 = idx.out; - prime_in1[done] = in1.done; + prime_in1[done] = in1.read_done; } group prime_in2 { - in2.content_en = 1'd1; + in2.read_en = 1'd1; in2.addr0 = idx.out; - prime_in2[done] = in2.done; + prime_in2[done] = in2.read_done; } // Computation @@ -66,10 +66,9 @@ component main() -> () { // Write to output group write { out.addr0 = 1'd0; - out.content_en = 1'd1; out.write_en = 1'd1; out.write_data = tmp.out; - write[done] = out.done; + write[done] = out.write_done; } } control { diff --git a/tests/correctness/static-islands/seq-mem-dot-product.futil b/tests/correctness/static-islands/seq-mem-dot-product.futil index 2bd501ded9..0d0dac3aa3 100644 --- a/tests/correctness/static-islands/seq-mem-dot-product.futil +++ b/tests/correctness/static-islands/seq-mem-dot-product.futil @@ -34,14 +34,14 @@ component main() -> () { // Prime memories for reading group prime_in1 { - in1.content_en = 1'd1; + in1.read_en = 1'd1; in1.addr0 = idx.out; - prime_in1[done] = in1.done; + prime_in1[done] = in1.read_done; } group prime_in2 { - in2.content_en = 1'd1; + in2.read_en = 1'd1; in2.addr0 = idx.out; - prime_in2[done] = in2.done; + prime_in2[done] = in2.read_done; } // Computation @@ -61,10 +61,9 @@ component main() -> () { // Write to output group write { out.addr0 = 1'd0; - out.content_en = 1'd1; out.write_en = 1'd1; out.write_data = tmp.out; - write[done] = out.done; + write[done] = out.write_done; } } control { diff --git a/tests/errors/no-drive.expect b/tests/errors/no-drive.expect index 6c4a4a7e75..a68436f9a5 100644 --- a/tests/errors/no-drive.expect +++ b/tests/errors/no-drive.expect @@ -3,4 +3,6 @@ ---STDERR--- Error: tests/errors/no-drive.futil 9 | group no_drive { - | ^^^^^^^^^^^^^^^^ [Papercut] Required signal not driven inside the group. When writing to the port `r.in', the ports [r.write_en] must also be written to. The primitive type `std_reg' specifies this using a @write_together spec. + | ^^^^^^^^^^^^^^^^ [Papercut] Required signal not driven inside the group. +When writing to the port `r.in', the ports [r.write_en] must also be written to. +The primitive type `std_reg' requires this invariant. diff --git a/tests/errors/papercut/multi-done.expect b/tests/errors/papercut/multi-done.expect index ec53a5bb70..2205081840 100644 --- a/tests/errors/papercut/multi-done.expect +++ b/tests/errors/papercut/multi-done.expect @@ -1,6 +1,4 @@ ---CODE--- 1 ---STDERR--- -Error: tests/errors/papercut/multi-done.futil -10 | read_done = mem_0.read_done; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Undefined port name: read_done +Error: [Papercut] Component `mem_0_comp` has an empty control program and does not assign to the done port `write_done`. Without an assignment to the done port, the component cannot return control flow. diff --git a/tests/errors/papercut/multi-done.futil b/tests/errors/papercut/multi-done.futil index de825346fe..6cf6aecf0f 100644 --- a/tests/errors/papercut/multi-done.futil +++ b/tests/errors/papercut/multi-done.futil @@ -6,7 +6,7 @@ component mem_0_comp<"toplevel"=1>(addr0: 3, @go read_en: 1, write_data: 32, @go wires { mem_0.clk = clk; read_data = mem_0.read_data; - mem_0.content_en = read_en; + mem_0.read_en = read_en; read_done = mem_0.read_done; mem_0.addr0 = addr0; mem_0.write_data = write_data; diff --git a/tests/errors/papercut/read-missing-write-comb.expect b/tests/errors/papercut/read-missing-write-comb.expect index 762173ca2d..e7c11b899e 100644 --- a/tests/errors/papercut/read-missing-write-comb.expect +++ b/tests/errors/papercut/read-missing-write-comb.expect @@ -4,5 +4,5 @@ Error: tests/errors/papercut/read-missing-write-comb.futil 11 | comb group check { | ^^^^^^^^^^^^^^^^^^ [Papercut] Required signal not driven inside the group. -When reading the port `mem.read_data', the ports [mem.addr0] must be written to. +When read the port `mem.read_data', the ports [mem.addr0] must be written to. The primitive type `comb_mem_d1' requires this invariant. diff --git a/tests/errors/papercut/read-missing-write.expect b/tests/errors/papercut/read-missing-write.expect index d544c1a271..228667fd52 100644 --- a/tests/errors/papercut/read-missing-write.expect +++ b/tests/errors/papercut/read-missing-write.expect @@ -4,5 +4,5 @@ Error: tests/errors/papercut/read-missing-write.futil 11 | group incr { | ^^^^^^^^^^^^ [Papercut] Required signal not driven inside the group. -When reading the port `mem.read_data', the ports [mem.addr0] must be written to. +When read the port `mem.read_data', the ports [mem.addr0] must be written to. The primitive type `comb_mem_d1' requires this invariant. diff --git a/tests/frontend/dahlia/combine.expect b/tests/frontend/dahlia/combine.expect index 35d968ef8e..d4d9e5cce7 100644 --- a/tests/frontend/dahlia/combine.expect +++ b/tests/frontend/dahlia/combine.expect @@ -26,10 +26,10 @@ component main() -> () { } group let1<"promotable"=2> { acc_0.in = A.read_data; - acc_0.write_en = A.done; + acc_0.write_en = A.read_done; let1[done] = acc_0.done; - A.content_en = 1'd1; A.addr0 = i0.out; + A.read_en = 1'd1; } group upd0<"promotable"=1> { res_0.write_en = 1'd1; diff --git a/tests/frontend/dahlia/dot-func.expect b/tests/frontend/dahlia/dot-func.expect index a52d267efa..9363646fa5 100644 --- a/tests/frontend/dahlia/dot-func.expect +++ b/tests/frontend/dahlia/dot-func.expect @@ -29,17 +29,17 @@ component dot() -> () { } group let1<"promotable"=2> { A_read0_0.in = A.read_data; - A_read0_0.write_en = A.done; + A_read0_0.write_en = A.read_done; let1[done] = A_read0_0.done; - A.content_en = 1'd1; A.addr0 = i0.out; + A.read_en = 1'd1; } group let2<"promotable"=2> { B_read0_0.in = B.read_data; - B_read0_0.write_en = B.done; + B_read0_0.write_en = B.read_done; let2[done] = B_read0_0.done; - B.content_en = 1'd1; B.addr0 = i0.out; + B.read_en = 1'd1; } group let3<"promotable"=4> { bin_read0_0.in = mult_pipe0.out; @@ -50,11 +50,10 @@ component dot() -> () { mult_pipe0.go = !mult_pipe0.done ? 1'd1; } group upd0<"promotable"=1> { - out.content_en = 1'd1; out.addr0 = i0.out; out.write_en = 1'd1; out.write_data = bin_read0_0.out; - upd0[done] = out.done; + upd0[done] = out.write_done; } group upd1<"promotable"=1> { i0.write_en = 1'd1; diff --git a/tests/frontend/dahlia/invoke-memory.expect b/tests/frontend/dahlia/invoke-memory.expect index 89e8ae49e0..2c868faba3 100644 --- a/tests/frontend/dahlia/invoke-memory.expect +++ b/tests/frontend/dahlia/invoke-memory.expect @@ -22,17 +22,16 @@ component mem_copy(length: 3) -> () { } group let1<"promotable"=2> { src_read0_0.in = src.read_data; - src_read0_0.write_en = src.done; + src_read0_0.write_en = src.read_done; let1[done] = src_read0_0.done; - src.content_en = 1'd1; src.addr0 = i_0.out; + src.read_en = 1'd1; } group upd0<"promotable"=1> { - dest.content_en = 1'd1; dest.addr0 = i_0.out; dest.write_en = 1'd1; dest.write_data = src_read0_0.out; - upd0[done] = dest.done; + upd0[done] = dest.write_done; } } control { diff --git a/tests/frontend/dahlia/matadd-fixed-point.expect b/tests/frontend/dahlia/matadd-fixed-point.expect index 2c489e0057..c631be0b1a 100644 --- a/tests/frontend/dahlia/matadd-fixed-point.expect +++ b/tests/frontend/dahlia/matadd-fixed-point.expect @@ -43,29 +43,28 @@ component main() -> () { } group let2<"promotable"=2> { a0_0_read0_0.in = a0_0.read_data; - a0_0_read0_0.write_en = a0_0.done; + a0_0_read0_0.write_en = a0_0.read_done; let2[done] = a0_0_read0_0.done; - a0_0.content_en = 1'd1; a0_0.addr1 = j0.out; a0_0.addr0 = i0.out; + a0_0.read_en = 1'd1; } group let3<"promotable"=2> { b0_0_read0_0.in = b0_0.read_data; - b0_0_read0_0.write_en = b0_0.done; + b0_0_read0_0.write_en = b0_0.read_done; let3[done] = b0_0_read0_0.done; - b0_0.content_en = 1'd1; b0_0.addr1 = j0.out; b0_0.addr0 = i0.out; + b0_0.read_en = 1'd1; } group upd0<"promotable"=1> { - result0_0.content_en = 1'd1; result0_0.addr1 = j0.out; result0_0.addr0 = i0.out; result0_0.write_en = 1'd1; add0.left = a0_0_read0_0.out; add0.right = b0_0_read0_0.out; result0_0.write_data = add0.out; - upd0[done] = result0_0.done; + upd0[done] = result0_0.write_done; } group upd1<"promotable"=1> { j0.write_en = 1'd1; diff --git a/tests/frontend/dahlia/memory.expect b/tests/frontend/dahlia/memory.expect index ba9ecce9f6..0e9773a1a3 100644 --- a/tests/frontend/dahlia/memory.expect +++ b/tests/frontend/dahlia/memory.expect @@ -18,28 +18,25 @@ component main() -> () { } wires { group upd0<"promotable"=1> { - A.content_en = 1'd1; A.addr0 = const1.out; A.write_en = 1'd1; A.write_data = const0.out; - upd0[done] = A.done; + upd0[done] = A.write_done; } group upd1<"promotable"=1> { - B.content_en = 1'd1; B.addr1 = const4.out; B.addr0 = const3.out; B.write_en = 1'd1; B.write_data = const2.out; - upd1[done] = B.done; + upd1[done] = B.write_done; } group upd2<"promotable"=1> { - C.content_en = 1'd1; C.addr2 = const8.out; C.addr1 = const7.out; C.addr0 = const6.out; C.write_en = 1'd1; C.write_data = const5.out; - upd2[done] = C.done; + upd2[done] = C.write_done; } } control { diff --git a/tests/frontend/dahlia/signed_dotproduct.expect b/tests/frontend/dahlia/signed_dotproduct.expect index 1fec16e24e..d737884616 100644 --- a/tests/frontend/dahlia/signed_dotproduct.expect +++ b/tests/frontend/dahlia/signed_dotproduct.expect @@ -40,19 +40,19 @@ component main() -> () { } group let2<"promotable"=2> { a0_read0_0.in = a0.read_data; - a0_read0_0.write_en = a0.done; + a0_read0_0.write_en = a0.read_done; let2[done] = a0_read0_0.done; - a0.content_en = 1'd1; a0.addr0 = slice0.out; slice0.in = i0.out; + a0.read_en = 1'd1; } group let3<"promotable"=2> { b0_read0_0.in = b0.read_data; - b0_read0_0.write_en = b0.done; + b0_read0_0.write_en = b0.read_done; let3[done] = b0_read0_0.done; - b0.content_en = 1'd1; b0.addr0 = slice1.out; slice1.in = i0.out; + b0.read_en = 1'd1; } group let4<"promotable"=4> { bin_read0_0.in = mult_pipe0.out; diff --git a/tests/frontend/dahlia/unroll.expect b/tests/frontend/dahlia/unroll.expect index b461a22955..367e11f3f8 100644 --- a/tests/frontend/dahlia/unroll.expect +++ b/tests/frontend/dahlia/unroll.expect @@ -38,34 +38,34 @@ component main() -> () { let0[done] = i0.done; } group upd0<"promotable"=2> { - acc_00.write_en = A0.done; - A0.content_en = 1'd1; + acc_00.write_en = A0.read_done; A0.addr0 = slice0.out; slice0.in = i0.out; + A0.read_en = 1'd1; acc_00.in = A0.read_data; upd0[done] = acc_00.done; } group upd1<"promotable"=2> { - acc_10.write_en = A1.done; - A1.content_en = 1'd1; + acc_10.write_en = A1.read_done; A1.addr0 = slice1.out; slice1.in = i0.out; + A1.read_en = 1'd1; acc_10.in = A1.read_data; upd1[done] = acc_10.done; } group upd2<"promotable"=2> { - acc_20.write_en = A2.done; - A2.content_en = 1'd1; + acc_20.write_en = A2.read_done; A2.addr0 = slice2.out; slice2.in = i0.out; + A2.read_en = 1'd1; acc_20.in = A2.read_data; upd2[done] = acc_20.done; } group upd3<"promotable"=2> { - acc_30.write_en = A3.done; - A3.content_en = 1'd1; + acc_30.write_en = A3.read_done; A3.addr0 = slice3.out; slice3.in = i0.out; + A3.read_en = 1'd1; acc_30.in = A3.read_data; upd3[done] = acc_30.done; } diff --git a/tests/frontend/relay/batch_flatten-same-dimensions.expect b/tests/frontend/relay/batch_flatten-same-dimensions.expect index e9d2628959..3babccb728 100644 --- a/tests/frontend/relay/batch_flatten-same-dimensions.expect +++ b/tests/frontend/relay/batch_flatten-same-dimensions.expect @@ -50,19 +50,18 @@ component batch_flatten_2x4096() -> () { } group let3<"promotable"=2> { x_read0_0.in = x.read_data; - x_read0_0.write_en = x.done; + x_read0_0.write_en = x.read_done; let3[done] = x_read0_0.done; - x.content_en = 1'd1; x.addr1 = __j0.out; x.addr0 = __i0.out; + x.read_en = 1'd1; } group upd0<"promotable"=1> { - x1.content_en = 1'd1; x1.addr1 = __k_0.out; x1.addr0 = __i0.out; x1.write_en = 1'd1; x1.write_data = x_read0_0.out; - upd0[done] = x1.done; + upd0[done] = x1.write_done; } group upd1<"promotable"=1> { __k_0.write_en = 1'd1; diff --git a/tests/frontend/relay/batch_flatten.expect b/tests/frontend/relay/batch_flatten.expect index a59a05d963..8b4a51f526 100644 --- a/tests/frontend/relay/batch_flatten.expect +++ b/tests/frontend/relay/batch_flatten.expect @@ -65,20 +65,19 @@ component batch_flatten_1x4() -> () { } group let4<"promotable"=2> { x_read0_0.in = x.read_data; - x_read0_0.write_en = x.done; + x_read0_0.write_en = x.read_done; let4[done] = x_read0_0.done; - x.content_en = 1'd1; x.addr2 = __k0.out; x.addr1 = __j0.out; x.addr0 = __i0.out; + x.read_en = 1'd1; } group upd0<"promotable"=1> { - x1.content_en = 1'd1; x1.addr1 = __l_0.out; x1.addr0 = __i0.out; x1.write_en = 1'd1; x1.write_data = x_read0_0.out; - upd0[done] = x1.done; + upd0[done] = x1.write_done; } group upd1<"promotable"=1> { __l_0.write_en = 1'd1; diff --git a/tests/frontend/relay/batch_matmul.expect b/tests/frontend/relay/batch_matmul.expect index 4a29bba8c1..fead34bc00 100644 --- a/tests/frontend/relay/batch_matmul.expect +++ b/tests/frontend/relay/batch_matmul.expect @@ -105,12 +105,12 @@ component batch_matmul_4x7x7() -> () { } group let11<"promotable"=2> { red_read00.in = x.read_data; - red_read00.write_en = x.done; + red_read00.write_en = x.read_done; let11[done] = red_read00.done; - x.content_en = 1'd1; x.addr2 = __j1.out; x.addr1 = __i1.out; x.addr0 = __batch1.out; + x.read_en = 1'd1; } group let2<"promotable"=1> { __j0.in = const4.out; @@ -119,12 +119,12 @@ component batch_matmul_4x7x7() -> () { } group let3<"promotable"=2> { b_read0_0.in = b.read_data; - b_read0_0.write_en = b.done; + b_read0_0.write_en = b.read_done; let3[done] = b_read0_0.done; - b.content_en = 1'd1; b.addr2 = __j0.out; b.addr1 = __i0.out; b.addr0 = __batch0.out; + b.read_en = 1'd1; } group let4<"promotable"=1> { __batch1.in = const9.out; @@ -148,12 +148,12 @@ component batch_matmul_4x7x7() -> () { } group let8<"promotable"=2> { a_read0_0.in = a.read_data; - a_read0_0.write_en = a.done; + a_read0_0.write_en = a.read_done; let8[done] = a_read0_0.done; - a.content_en = 1'd1; a.addr2 = __k0.out; a.addr1 = __i1.out; a.addr0 = __batch1.out; + a.read_en = 1'd1; } group let9<"promotable"=4> { bin_read0_0.in = mult_pipe0.out; @@ -164,13 +164,12 @@ component batch_matmul_4x7x7() -> () { mult_pipe0.go = !mult_pipe0.done ? 1'd1; } group upd0<"promotable"=1> { - __transpose_b0_0_0.content_en = 1'd1; __transpose_b0_0_0.addr2 = __i0.out; __transpose_b0_0_0.addr1 = __j0.out; __transpose_b0_0_0.addr0 = __batch0.out; __transpose_b0_0_0.write_en = 1'd1; __transpose_b0_0_0.write_data = b_read0_0.out; - upd0[done] = __transpose_b0_0_0.done; + upd0[done] = __transpose_b0_0_0.write_done; } group upd1<"promotable"=1> { __j0.write_en = 1'd1; @@ -194,16 +193,15 @@ component batch_matmul_4x7x7() -> () { upd3[done] = __batch0.done; } group upd4<"promotable"=2> { - __transpose_b_read0_0.write_en = __transpose_b0_0_0.done; - __transpose_b0_0_0.content_en = 1'd1; + __transpose_b_read0_0.write_en = __transpose_b0_0_0.read_done; __transpose_b0_0_0.addr2 = __j1.out; __transpose_b0_0_0.addr1 = __k0.out; __transpose_b0_0_0.addr0 = __batch1.out; + __transpose_b0_0_0.read_en = 1'd1; __transpose_b_read0_0.in = __transpose_b0_0_0.read_data; upd4[done] = __transpose_b_read0_0.done; } group upd5<"promotable"=1> { - x.content_en = 1'd1; x.addr2 = __j1.out; x.addr1 = __i1.out; x.addr0 = __batch1.out; @@ -211,7 +209,7 @@ component batch_matmul_4x7x7() -> () { add3.left = red_read00.out; add3.right = __product_0.out; x.write_data = add3.out; - upd5[done] = x.done; + upd5[done] = x.write_done; } group upd6<"promotable"=1> { __k0.write_en = 1'd1; diff --git a/tests/frontend/relay/bias_add.expect b/tests/frontend/relay/bias_add.expect index 3be156f32a..afd34c5ab9 100644 --- a/tests/frontend/relay/bias_add.expect +++ b/tests/frontend/relay/bias_add.expect @@ -74,23 +74,22 @@ component bias_add_1x64x512x256() -> () { } group let4<"promotable"=2> { x_read0_0.in = x.read_data; - x_read0_0.write_en = x.done; + x_read0_0.write_en = x.read_done; let4[done] = x_read0_0.done; - x.content_en = 1'd1; x.addr3 = __l0.out; x.addr2 = __k0.out; x.addr1 = __j0.out; x.addr0 = __i0.out; + x.read_en = 1'd1; } group let5<"promotable"=2> { bias_read0_0.in = bias.read_data; - bias_read0_0.write_en = bias.done; + bias_read0_0.write_en = bias.read_done; let5[done] = bias_read0_0.done; - bias.content_en = 1'd1; bias.addr0 = __j0.out; + bias.read_en = 1'd1; } group upd0<"promotable"=1> { - x1.content_en = 1'd1; x1.addr3 = __l0.out; x1.addr2 = __k0.out; x1.addr1 = __j0.out; @@ -99,7 +98,7 @@ component bias_add_1x64x512x256() -> () { add0.left = x_read0_0.out; add0.right = bias_read0_0.out; x1.write_data = add0.out; - upd0[done] = x1.done; + upd0[done] = x1.write_done; } group upd1<"promotable"=1> { __l0.write_en = 1'd1; diff --git a/tests/frontend/relay/broadcast.expect b/tests/frontend/relay/broadcast.expect index c3546dc728..93b0f564f5 100644 --- a/tests/frontend/relay/broadcast.expect +++ b/tests/frontend/relay/broadcast.expect @@ -45,29 +45,28 @@ component add_2x4() -> () { } group let2<"promotable"=2> { x_read0_0.in = x.read_data; - x_read0_0.write_en = x.done; + x_read0_0.write_en = x.read_done; let2[done] = x_read0_0.done; - x.content_en = 1'd1; x.addr1 = __j0.out; x.addr0 = __i0.out; + x.read_en = 1'd1; } group let3<"promotable"=2> { y_read0_0.in = y.read_data; - y_read0_0.write_en = y.done; + y_read0_0.write_en = y.read_done; let3[done] = y_read0_0.done; - y.content_en = 1'd1; y.addr1 = const4.out; y.addr0 = __i0.out; + y.read_en = 1'd1; } group upd0<"promotable"=1> { - x1.content_en = 1'd1; x1.addr1 = __j0.out; x1.addr0 = __i0.out; x1.write_en = 1'd1; add0.left = x_read0_0.out; add0.right = y_read0_0.out; x1.write_data = add0.out; - upd0[done] = x1.done; + upd0[done] = x1.write_done; } group upd1<"promotable"=1> { __j0.write_en = 1'd1; diff --git a/tests/frontend/relay/constant-multiply.expect b/tests/frontend/relay/constant-multiply.expect index 83930a3ead..e843c91274 100644 --- a/tests/frontend/relay/constant-multiply.expect +++ b/tests/frontend/relay/constant-multiply.expect @@ -28,10 +28,10 @@ component multiply_1(x1: 32) -> () { } group let1<"promotable"=2> { x_read0_0.in = x.read_data; - x_read0_0.write_en = x.done; + x_read0_0.write_en = x.read_done; let1[done] = x_read0_0.done; - x.content_en = 1'd1; x.addr0 = __i0.out; + x.read_en = 1'd1; } group let2<"promotable"=4> { bin_read0_0.in = mult_pipe0.out; @@ -42,11 +42,10 @@ component multiply_1(x1: 32) -> () { mult_pipe0.go = !mult_pipe0.done ? 1'd1; } group upd0<"promotable"=1> { - x2.content_en = 1'd1; x2.addr0 = __i0.out; x2.write_en = 1'd1; x2.write_data = bin_read0_0.out; - upd0[done] = x2.done; + upd0[done] = x2.write_done; } group upd1<"promotable"=1> { __i0.write_en = 1'd1; diff --git a/tests/frontend/relay/conv2d.expect b/tests/frontend/relay/conv2d.expect index 049a320f90..b755a86ced 100644 --- a/tests/frontend/relay/conv2d.expect +++ b/tests/frontend/relay/conv2d.expect @@ -173,9 +173,8 @@ component conv2d_5x512x14x14() -> () { } group let13<"promotable"=2> { data_read0_0.in = data.read_data; - data_read0_0.write_en = data.done; + data_read0_0.write_en = data.read_done; let13[done] = data_read0_0.done; - data.content_en = 1'd1; data.addr3 = slice3.out; slice3.in = sub1.out; sub1.left = __kernel_x_0.out; @@ -188,12 +187,12 @@ component conv2d_5x512x14x14() -> () { slice1.in = __k0.out; data.addr0 = slice0.out; slice0.in = __b0.out; + data.read_en = 1'd1; } group let14<"promotable"=2> { weight_read0_0.in = weight.read_data; - weight_read0_0.write_en = weight.done; + weight_read0_0.write_en = weight.read_done; let14[done] = weight_read0_0.done; - weight.content_en = 1'd1; weight.addr3 = slice7.out; slice7.in = __dx0.out; weight.addr2 = slice6.out; @@ -202,6 +201,7 @@ component conv2d_5x512x14x14() -> () { slice5.in = __k0.out; weight.addr0 = slice4.out; slice4.in = __c0.out; + weight.read_en = 1'd1; } group let15<"promotable"=4> { bin_read2_0.in = mult_pipe2.out; @@ -290,7 +290,6 @@ component conv2d_5x512x14x14() -> () { upd4[done] = __k0.done; } group upd5<"promotable"=1> { - x.content_en = 1'd1; x.addr3 = slice11.out; slice11.in = __x0.out; x.addr2 = slice10.out; @@ -301,7 +300,7 @@ component conv2d_5x512x14x14() -> () { slice8.in = __b0.out; x.write_en = 1'd1; x.write_data = __sum_0.out; - upd5[done] = x.done; + upd5[done] = x.write_done; } group upd6<"promotable"=1> { __x0.write_en = 1'd1; diff --git a/tests/frontend/relay/dense.expect b/tests/frontend/relay/dense.expect index 5fbd43f9af..39d9f12c7b 100644 --- a/tests/frontend/relay/dense.expect +++ b/tests/frontend/relay/dense.expect @@ -63,19 +63,19 @@ component dense_1x10() -> () { } group let3<"promotable"=2> { x_read0_0.in = x.read_data; - x_read0_0.write_en = x.done; + x_read0_0.write_en = x.read_done; let3[done] = x_read0_0.done; - x.content_en = 1'd1; x.addr1 = __k0.out; x.addr0 = __i0.out; + x.read_en = 1'd1; } group let4<"promotable"=2> { y_read0_0.in = y.read_data; - y_read0_0.write_en = y.done; + y_read0_0.write_en = y.read_done; let4[done] = y_read0_0.done; - y.content_en = 1'd1; y.addr1 = __k0.out; y.addr0 = __j0.out; + y.read_en = 1'd1; } group let5<"promotable"=4> { bin_read0_0.in = mult_pipe0.out; @@ -92,21 +92,20 @@ component dense_1x10() -> () { } group let7<"promotable"=2> { red_read00.in = x1.read_data; - red_read00.write_en = x1.done; + red_read00.write_en = x1.read_done; let7[done] = red_read00.done; - x1.content_en = 1'd1; x1.addr1 = __j0.out; x1.addr0 = __i0.out; + x1.read_en = 1'd1; } group upd0<"promotable"=1> { - x1.content_en = 1'd1; x1.addr1 = __j0.out; x1.addr0 = __i0.out; x1.write_en = 1'd1; add0.left = red_read00.out; add0.right = __product_0.out; x1.write_data = add0.out; - upd0[done] = x1.done; + upd0[done] = x1.write_done; } group upd1<"promotable"=1> { __k0.write_en = 1'd1; diff --git a/tests/frontend/relay/duplicate-relay-call.expect b/tests/frontend/relay/duplicate-relay-call.expect index 3fc72d25b2..13b64c01dc 100644 --- a/tests/frontend/relay/duplicate-relay-call.expect +++ b/tests/frontend/relay/duplicate-relay-call.expect @@ -43,21 +43,20 @@ component negative_2x2() -> () { } group let2<"promotable"=2> { x_read0_0.in = x.read_data; - x_read0_0.write_en = x.done; + x_read0_0.write_en = x.read_done; let2[done] = x_read0_0.done; - x.content_en = 1'd1; x.addr1 = __j0.out; x.addr0 = __i0.out; + x.read_en = 1'd1; } group upd0<"promotable"=1> { - x1.content_en = 1'd1; x1.addr1 = __j0.out; x1.addr0 = __i0.out; x1.write_en = 1'd1; sub0.left = const4.out; sub0.right = x_read0_0.out; x1.write_data = sub0.out; - upd0[done] = x1.done; + upd0[done] = x1.write_done; } group upd1<"promotable"=1> { __j0.write_en = 1'd1; diff --git a/tests/frontend/relay/max_pool2d.expect b/tests/frontend/relay/max_pool2d.expect index 2b546206e5..0df1a39909 100644 --- a/tests/frontend/relay/max_pool2d.expect +++ b/tests/frontend/relay/max_pool2d.expect @@ -130,9 +130,8 @@ component max_pool2d_2x2x2x2() -> () { } group let13<"promotable"=2> { __current_0.in = data.read_data; - __current_0.write_en = data.done; + __current_0.write_en = data.read_done; let13[done] = __current_0.done; - data.content_en = 1'd1; data.addr3 = slice7.out; slice7.in = __pool_x_0.out; data.addr2 = slice6.out; @@ -141,6 +140,7 @@ component max_pool2d_2x2x2x2() -> () { slice5.in = __c0.out; data.addr0 = slice4.out; slice4.in = __b0.out; + data.read_en = 1'd1; } group let2<"promotable"=1> { __y0.in = const4.out; @@ -180,9 +180,8 @@ component max_pool2d_2x2x2x2() -> () { } group let8<"promotable"=2> { __max_0.in = data.read_data; - __max_0.write_en = data.done; + __max_0.write_en = data.read_done; let8[done] = __max_0.done; - data.content_en = 1'd1; data.addr3 = slice3.out; slice3.in = __stride_x_0.out; data.addr2 = slice2.out; @@ -191,6 +190,7 @@ component max_pool2d_2x2x2x2() -> () { slice1.in = __c0.out; data.addr0 = slice0.out; slice0.in = __b0.out; + data.read_en = 1'd1; } group let9<"promotable"=1> { __m0.in = const10.out; @@ -217,7 +217,6 @@ component max_pool2d_2x2x2x2() -> () { upd2[done] = __m0.done; } group upd3<"promotable"=1> { - result.content_en = 1'd1; result.addr3 = slice11.out; slice11.in = __x0.out; result.addr2 = slice10.out; @@ -228,7 +227,7 @@ component max_pool2d_2x2x2x2() -> () { slice8.in = __b0.out; result.write_en = 1'd1; result.write_data = __max_0.out; - upd3[done] = result.done; + upd3[done] = result.write_done; } group upd4<"promotable"=1> { __x0.write_en = 1'd1; diff --git a/tests/frontend/relay/negative.expect b/tests/frontend/relay/negative.expect index 105bdf3184..5770fa359c 100644 --- a/tests/frontend/relay/negative.expect +++ b/tests/frontend/relay/negative.expect @@ -28,19 +28,18 @@ component negative_4() -> () { } group let1<"promotable"=2> { x_read0_0.in = x.read_data; - x_read0_0.write_en = x.done; + x_read0_0.write_en = x.read_done; let1[done] = x_read0_0.done; - x.content_en = 1'd1; x.addr0 = __i0.out; + x.read_en = 1'd1; } group upd0<"promotable"=1> { - x1.content_en = 1'd1; x1.addr0 = __i0.out; x1.write_en = 1'd1; sub0.left = const2.out; sub0.right = x_read0_0.out; x1.write_data = sub0.out; - upd0[done] = x1.done; + upd0[done] = x1.write_done; } group upd1<"promotable"=1> { __i0.write_en = 1'd1; diff --git a/tests/frontend/relay/relu.expect b/tests/frontend/relay/relu.expect index c687b4eaa1..3031812ea1 100644 --- a/tests/frontend/relay/relu.expect +++ b/tests/frontend/relay/relu.expect @@ -79,43 +79,41 @@ component relu_2x4x8x32() -> () { } group let4<"promotable"=2> { x_read0_0.in = x.read_data; - x_read0_0.write_en = x.done; + x_read0_0.write_en = x.read_done; let4[done] = x_read0_0.done; - x.content_en = 1'd1; x.addr3 = __l0.out; x.addr2 = __k0.out; x.addr1 = __j0.out; x.addr0 = __i0.out; + x.read_en = 1'd1; } group let5<"promotable"=2> { x_read1_0.in = x.read_data; - x_read1_0.write_en = x.done; + x_read1_0.write_en = x.read_done; let5[done] = x_read1_0.done; - x.content_en = 1'd1; x.addr3 = __l0.out; x.addr2 = __k0.out; x.addr1 = __j0.out; x.addr0 = __i0.out; + x.read_en = 1'd1; } group upd0<"promotable"=1> { - x1.content_en = 1'd1; x1.addr3 = __l0.out; x1.addr2 = __k0.out; x1.addr1 = __j0.out; x1.addr0 = __i0.out; x1.write_en = 1'd1; x1.write_data = x_read1_0.out; - upd0[done] = x1.done; + upd0[done] = x1.write_done; } group upd1<"promotable"=1> { - x1.content_en = 1'd1; x1.addr3 = __l0.out; x1.addr2 = __k0.out; x1.addr1 = __j0.out; x1.addr0 = __i0.out; x1.write_en = 1'd1; x1.write_data = fp_const1.out; - upd1[done] = x1.done; + upd1[done] = x1.write_done; } group upd2<"promotable"=1> { __l0.write_en = 1'd1; diff --git a/tests/frontend/relay/reshape.expect b/tests/frontend/relay/reshape.expect index 85acd332c8..51e398d784 100644 --- a/tests/frontend/relay/reshape.expect +++ b/tests/frontend/relay/reshape.expect @@ -81,21 +81,20 @@ component reshape_1x8() -> () { } group let5<"promotable"=2> { x_read0_0.in = x.read_data; - x_read0_0.write_en = x.done; + x_read0_0.write_en = x.read_done; let5[done] = x_read0_0.done; - x.content_en = 1'd1; x.addr3 = __l0.out; x.addr2 = __k0.out; x.addr1 = __j0.out; x.addr0 = __i0.out; + x.read_en = 1'd1; } group upd0<"promotable"=1> { - x1.content_en = 1'd1; x1.addr1 = __m_0.out; x1.addr0 = const9.out; x1.write_en = 1'd1; x1.write_data = x_read0_0.out; - upd0[done] = x1.done; + upd0[done] = x1.write_done; } group upd1<"promotable"=1> { __m_0.write_en = 1'd1; diff --git a/tests/frontend/relay/softmax.expect b/tests/frontend/relay/softmax.expect index 37c9b68721..b663106657 100644 --- a/tests/frontend/relay/softmax.expect +++ b/tests/frontend/relay/softmax.expect @@ -85,11 +85,11 @@ component softmax_1x10() -> () { } group let0<"promotable"=2> { __max_0.in = x.read_data; - __max_0.write_en = x.done; + __max_0.write_en = x.read_done; let0[done] = __max_0.done; - x.content_en = 1'd1; x.addr1 = const1.out; x.addr0 = const0.out; + x.read_en = 1'd1; } group let1<"promotable"=1> { __i0.in = const2.out; @@ -108,11 +108,11 @@ component softmax_1x10() -> () { } group let12<"promotable"=2> { x_read3_0.in = x.read_data; - x_read3_0.write_en = x.done; + x_read3_0.write_en = x.read_done; let12[done] = x_read3_0.done; - x.content_en = 1'd1; x.addr1 = __k0.out; x.addr0 = __i1.out; + x.read_en = 1'd1; } group let13<"promotable"=1> { __t2_0.in = sub1.out; @@ -141,19 +141,19 @@ component softmax_1x10() -> () { } group let3<"promotable"=2> { x_read0_0.in = x.read_data; - x_read0_0.write_en = x.done; + x_read0_0.write_en = x.read_done; let3[done] = x_read0_0.done; - x.content_en = 1'd1; x.addr1 = __j0.out; x.addr0 = __i0.out; + x.read_en = 1'd1; } group let4<"promotable"=2> { x_read1_0.in = x.read_data; - x_read1_0.write_en = x.done; + x_read1_0.write_en = x.read_done; let4[done] = x_read1_0.done; - x.content_en = 1'd1; x.addr1 = __j0.out; x.addr0 = __i0.out; + x.read_en = 1'd1; } group let5<"promotable"=1> { __i1.in = const8.out; @@ -172,11 +172,11 @@ component softmax_1x10() -> () { } group let8<"promotable"=2> { x_read2_0.in = x.read_data; - x_read2_0.write_en = x.done; + x_read2_0.write_en = x.read_done; let8[done] = x_read2_0.done; - x.content_en = 1'd1; x.addr1 = __j1.out; x.addr0 = __i1.out; + x.read_en = 1'd1; } group let9<"promotable"=1> { __t0_0.in = sub0.out; @@ -219,12 +219,11 @@ component softmax_1x10() -> () { upd4[done] = __j1.done; } group upd5<"promotable"=1> { - x1.content_en = 1'd1; x1.addr1 = __k0.out; x1.addr0 = __i1.out; x1.write_en = 1'd1; x1.write_data = bin_read0_0.out; - upd5[done] = x1.done; + upd5[done] = x1.write_done; } group upd6<"promotable"=1> { __k0.write_en = 1'd1; diff --git a/tests/frontend/relay/sqrt.expect b/tests/frontend/relay/sqrt.expect index ed5d9a5281..c6b20dcb38 100644 --- a/tests/frontend/relay/sqrt.expect +++ b/tests/frontend/relay/sqrt.expect @@ -43,11 +43,11 @@ component sqrt_1x4() -> () { } group let2<"promotable"=2> { x_read0_0.in = x.read_data; - x_read0_0.write_en = x.done; + x_read0_0.write_en = x.read_done; let2[done] = x_read0_0.done; - x.content_en = 1'd1; x.addr1 = __j0.out; x.addr0 = __i0.out; + x.read_en = 1'd1; } group let3 { __tmp_0.in = sqrt0.out; @@ -55,12 +55,11 @@ component sqrt_1x4() -> () { let3[done] = __tmp_0.done; } group upd0<"promotable"=1> { - x1.content_en = 1'd1; x1.addr1 = __j0.out; x1.addr0 = __i0.out; x1.write_en = 1'd1; x1.write_data = __tmp_0.out; - upd0[done] = x1.done; + upd0[done] = x1.write_done; } group upd1<"promotable"=1> { __j0.write_en = 1'd1; diff --git a/tests/frontend/relay/tensor_add.expect b/tests/frontend/relay/tensor_add.expect index f195de4c66..6900f3583f 100644 --- a/tests/frontend/relay/tensor_add.expect +++ b/tests/frontend/relay/tensor_add.expect @@ -44,29 +44,28 @@ component add_2x4() -> () { } group let2<"promotable"=2> { x_read0_0.in = x.read_data; - x_read0_0.write_en = x.done; + x_read0_0.write_en = x.read_done; let2[done] = x_read0_0.done; - x.content_en = 1'd1; x.addr1 = __j0.out; x.addr0 = __i0.out; + x.read_en = 1'd1; } group let3<"promotable"=2> { y_read0_0.in = y.read_data; - y_read0_0.write_en = y.done; + y_read0_0.write_en = y.read_done; let3[done] = y_read0_0.done; - y.content_en = 1'd1; y.addr1 = __j0.out; y.addr0 = __i0.out; + y.read_en = 1'd1; } group upd0<"promotable"=1> { - x1.content_en = 1'd1; x1.addr1 = __j0.out; x1.addr0 = __i0.out; x1.write_en = 1'd1; add0.left = x_read0_0.out; add0.right = y_read0_0.out; x1.write_data = add0.out; - upd0[done] = x1.done; + upd0[done] = x1.write_done; } group upd1<"promotable"=1> { __j0.write_en = 1'd1; diff --git a/tests/passes/papercut-multi-done.expect b/tests/passes/papercut-multi-done.expect index 9b5c7a8488..5e37f8477a 100644 --- a/tests/passes/papercut-multi-done.expect +++ b/tests/passes/papercut-multi-done.expect @@ -1,16 +1,17 @@ import "primitives/memories/seq.futil"; -component mem_0_comp<"toplevel"=1>(addr0: 3, @go read_en: 1, write_data: 32, @go(2) write_en: 1, @clk clk: 1, @reset reset: 1) -> (read_data: 32, @done done: 1) { +component mem_0_comp<"toplevel"=1>(addr0: 3, @go read_en: 1, write_data: 32, @go(2) write_en: 1, @clk clk: 1, @reset reset: 1) -> (read_data: 32, @done read_done: 1, @done(2) write_done: 1) { cells { mem_0 = seq_mem_d1(32, 6, 3); } wires { mem_0.clk = clk; read_data = mem_0.read_data; - mem_0.content_en = read_en; - done = mem_0.done; + mem_0.read_en = read_en; + read_done = mem_0.read_done; mem_0.addr0 = addr0; mem_0.write_data = write_data; mem_0.write_en = write_en; + write_done = mem_0.write_done; } control {} } diff --git a/tests/passes/papercut-multi-done.futil b/tests/passes/papercut-multi-done.futil index 0943af98f4..7084ea5166 100644 --- a/tests/passes/papercut-multi-done.futil +++ b/tests/passes/papercut-multi-done.futil @@ -2,18 +2,19 @@ import "primitives/memories/seq.futil"; -component mem_0_comp<"toplevel"=1>(addr0: 3, @go read_en: 1, write_data: 32, @go(2) write_en: 1, @clk clk: 1, @reset reset: 1) -> (read_data: 32, @done done: 1) { +component mem_0_comp<"toplevel"=1>(addr0: 3, @go read_en: 1, write_data: 32, @go(2) write_en: 1, @clk clk: 1, @reset reset: 1) -> (read_data: 32, @done read_done: 1, @done(2) write_done: 1) { cells { mem_0 = seq_mem_d1(32, 6, 3); } wires { mem_0.clk = clk; read_data = mem_0.read_data; - mem_0.content_en = read_en; - done = mem_0.done; + mem_0.read_en = read_en; + read_done = mem_0.read_done; mem_0.addr0 = addr0; mem_0.write_data = write_data; mem_0.write_en = write_en; + write_done = mem_0.write_done; } control { } diff --git a/yxi/axi-calyx/axi-combined-calyx.futil b/yxi/axi-calyx/axi-combined-calyx.futil index d116a9b248..6e5b1db556 100644 --- a/yxi/axi-calyx/axi-combined-calyx.futil +++ b/yxi/axi-calyx/axi-combined-calyx.futil @@ -196,7 +196,7 @@ component m_read_channel( wires{ RREADY = is_rdy.out; - data_received.content_en = 1'b0; + data_received.read_en = 1'b0; // NOTE: xVALID signals must be high until xREADY is high as well, so this works // because if xREADY is high (is_rdy.out) then RVALID being high makes 1 flip @@ -247,7 +247,7 @@ component m_read_channel( data_received.addr0 = curr_addr_internal_mem.out; data_received.write_en = 1'b1; data_received.write_data = read_data_reg.out; - receive_r_transfer[done] = data_received.done; + receive_r_transfer[done] = data_received.write_done; } @@ -324,17 +324,17 @@ component vec_add() -> () { } //modified upd0 and upd1 to use seq_mem correctly group upd0<"static"=2> { - A_read0_0.write_en = A0.done; + A_read0_0.write_en = A0.read_done; A0.addr0 = i0.out; - A0.content_en = 1'b1; + A0.read_en = 1'b1; A_read0_0.in = 1'd1 ? A0.read_data; upd0[done] = A_read0_0.done ? 1'd1; } //see comment for upd0 group upd1<"static"=2> { - B_read0_0.write_en = B0.done; + B_read0_0.write_en = B0.read_done; B0.addr0 = i0.out; - B0.content_en = 1'b1; + B0.read_en = 1'b1; B_read0_0.in = 1'd1 ? B0.read_data; upd1[done] = B_read0_0.done ? 1'd1; } @@ -344,7 +344,7 @@ component vec_add() -> () { add0.left = A_read0_0.out; add0.right = B_read0_0.out; Sum0.write_data = 1'd1 ? add0.out; - upd2[done] = Sum0.done ? 1'd1; + upd2[done] = Sum0.write_done ? 1'd1; } group upd3<"static"=1> { i0.write_en = 1'd1; @@ -590,7 +590,7 @@ component m_write_channel( // set data output based on curr_addr_internal_mem register internal_mem.addr0 = curr_addr_internal_mem.out; - internal_mem.content_en = 1'b1; + internal_mem.read_en = 1'b1; WDATA = internal_mem.read_data; //set wlast diff --git a/yxi/axi-calyx/axi-reads-calyx.futil b/yxi/axi-calyx/axi-reads-calyx.futil index 8bd5d6f349..b566cbe5c7 100644 --- a/yxi/axi-calyx/axi-reads-calyx.futil +++ b/yxi/axi-calyx/axi-reads-calyx.futil @@ -209,7 +209,7 @@ component m_read_channel( wires{ RREADY = is_rdy.out; - data_received.content_en = 1'b0; + data_received.read_en = 1'b0; group init_n_RLAST { n_RLAST.in = 1'b1; @@ -269,7 +269,7 @@ component m_read_channel( data_received.addr0 = curr_addr.out; data_received.write_en = 1'b1; data_received.write_data = read_data_reg.out; - receive_r_transfer[done] = data_received.done; + receive_r_transfer[done] = data_received.write_done; } diff --git a/yxi/axi-calyx/axi-writes-calyx.futil b/yxi/axi-calyx/axi-writes-calyx.futil index 150cc9be9c..402d9f8a48 100644 --- a/yxi/axi-calyx/axi-writes-calyx.futil +++ b/yxi/axi-calyx/axi-writes-calyx.futil @@ -243,13 +243,13 @@ component m_write_channel( } group write_to_internal{ - internal_mem.content_en = 1'b0; + internal_mem.read_en = 1'b0; internal_mem.write_en = 1'b1; internal_mem.addr0 = curr_addr.out; curr_addr_slice.in = curr_addr.out; internal_mem.write_data = curr_addr_slice.out; - write_to_internal[done] = internal_mem.done; + write_to_internal[done] = internal_mem.write_done; } group check_if_writes_done{ @@ -303,7 +303,7 @@ component m_write_channel( // set data output based on curr_addr register internal_mem.addr0 = curr_addr.out; - internal_mem.content_en = 1'b1; + internal_mem.read_en = 1'b1; WDATA = internal_mem.read_data; //set wlast