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After RTL modification related to the csi_byte_clk signal, we managed to bypass the routing error.
NOTE: For testing purposes only – the error still exists, we just masked it, and it is described in this issue. Modifications are placed in a separate file csi_rx_top_2.v.
After that, the tool reports a new issue related to IDELAYCTRL component.
ERROR: Found IDELAYCTRL but no I/ODELAYs in group default 2 warnings, 1 error make: *** [Makefile:69: error2.fasm] Error 255
Steps to reproduce:
Navigate to 3.build/openXC7, where the Makefile is located.
After RTL modification related to the csi_byte_clk signal, we managed to bypass the routing error.
After that, the tool reports a new issue related to IDELAYCTRL component.
ERROR: Found IDELAYCTRL but no I/ODELAYs in group default 2 warnings, 1 error make: *** [Makefile:69: error2.fasm] Error 255
Steps to reproduce:
make error2
@hansfbaier, @MikeReznikov Do you have any ideas on how to solve this problem?
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