Change in behavior between 3.3.2 and 3.4.0-RC3 for naming

[jackkoenig]

Type of issue: bug report

Impact: naming behavior change (back to old behavior)

Development Phase: request

Other information

If the current behavior is a bug, please provide the steps to reproduce the problem:

Given a somewhat weird (but useful) pattern:

import chisel3._
import chisel3.stage.ChiselStage

class Example(n: Int) extends MultiIOModule {
  val out = Seq.tabulate(n) { i =>
    val ioOpt = (if (i % 2 == 0) None else Some {
      val x = IO(Output(UInt(8.W)))
      x
    })
    ioOpt
  }
  
  out.foreach(_.foreach(_ := 0.U))
}

println((new ChiselStage).emitVerilog(new Example(4)))

The type of val out is Seq[Option[UInt]], this is actually very useful because the inner option allows us to skip indices in the namespace when there are Nones:

What is the current behavior?

In Chisel v3.4.0-RC3, this gives:

module Example(
  input        clock,
  input        reset,
  output [7:0] out_ioOpt_x,
  output [7:0] out_ioOpt_x_1
);
  assign out_ioOpt_x = 8'h0; // @[main.scala 15:27]
  assign out_ioOpt_x_1 = 8'h0; // @[main.scala 15:27]
endmodule

What is the expected behavior?

In Chisel v3.3.2, this gives:

module Example(
  input        clock,
  input        reset,
  output [7:0] out_1,
  output [7:0] out_3
);
  assign out_1 = 8'h0; // @[main.scala 15:27]
  assign out_3 = 8'h0; // @[main.scala 15:27]
endmodule

What is the use case for changing the behavior?

Restore previous (useful) naming behavior

[jackkoenig]

An example of what I suspect is the same issue happens in rocket-chip here: https://github.com/chipsalliance/rocket-chip/blob/c6b41bf5918bbafc7dccee70e208352e029d9505/src/main/scala/devices/debug/Periphery.scala#L112

Simple example of the bug: https://scastie.scala-lang.org/A2AN5lgAQHaRfWDFbOoyjQ

Example of a workaround: https://scastie.scala-lang.org/UQoz4TceRxCFQIWZx8S37A

[jackkoenig]

This issue stems from the behavior of autoSeed on ports:
https://github.com/freechipsproject/chisel3/blob/26deb7703389b78a9b2a61f7e191f3f0e2a6623b/core/src/main/scala/chisel3/Data.scala#L289

Basically, ports have special behavior where the first seed wins. The "first seed wins" is nice because it fixes #1352. It's not really clear how we both fix this issue and #1352.