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Add emitSystemVerilog method to ChiselStage #1534

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merged 1 commit into from
Jul 31, 2020

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tdb-alcorn
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Type of change: other enhancement

Impact: API addition (no impact on existing code)

Development Phase: implementation

Release Notes

Adds a method for emitting SystemVerilog to the top level API, which previously required a workaround of a few lines of code.

@tdb-alcorn tdb-alcorn requested a review from a team as a code owner July 30, 2020 22:55
@seldridge seldridge added this to the 3.4.0 milestone Jul 31, 2020
@seldridge seldridge added the Please Merge Accepted PRs that are ready to be merged. Useful when waiting on CI. label Jul 31, 2020
@mergify mergify bot merged commit 8990ca3 into chipsalliance:master Jul 31, 2020
jackkoenig pushed a commit that referenced this pull request Feb 28, 2023
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