From f65921161372180eb4a9ff742a3fe723dfe19a6c Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Sun, 28 Jan 2024 21:44:46 +0800 Subject: [PATCH 1/4] implement FirtoolOptions - Implement a simple data structure for FirtoolOptions - use it in panamalib - move panamaCIRCT out from converter --- panamaconverter/src/Convert.scala | 6 +- .../src/PanamaCIRCTConverter.scala | 13 ++- .../src/PanamaCIRCTPassManager.scala | 6 +- panamalib/src/FirtoolOptions.scala | 81 +++++++++++++++++ panamalib/src/PanamaFirtoolOption.scala | 91 +++++++++++++++++++ 5 files changed, 189 insertions(+), 8 deletions(-) create mode 100644 panamalib/src/FirtoolOptions.scala create mode 100644 panamalib/src/PanamaFirtoolOption.scala diff --git a/panamaconverter/src/Convert.scala b/panamaconverter/src/Convert.scala index 9f735ebeff9..e8da3826aa5 100644 --- a/panamaconverter/src/Convert.scala +++ b/panamaconverter/src/Convert.scala @@ -3,6 +3,7 @@ package chisel3.panamaconverter.stage import chisel3.panamaconverter.PanamaCIRCTConverter +import chisel3.panamalib.option.FirtoolOptions import chisel3.stage.ChiselCircuitAnnotation import chisel3.stage.phases.Elaborate import firrtl.AnnotationSeq @@ -10,6 +11,7 @@ import firrtl.annotations.NoTargetAnnotation import firrtl.options.{Dependency, Phase} case class PanamaCIRCTConverterAnnotation(converter: PanamaCIRCTConverter) extends NoTargetAnnotation +case class FirtoolOptionsAnnotation(firtoolOptions: FirtoolOptions) extends NoTargetAnnotation object Convert extends Phase { override def prerequisites = Seq(Dependency[Elaborate]) @@ -20,7 +22,9 @@ object Convert extends Phase { def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.flatMap { case c @ ChiselCircuitAnnotation(circuit) => - Seq(c, PanamaCIRCTConverterAnnotation(PanamaCIRCTConverter.convert(circuit))) + Seq(c, PanamaCIRCTConverterAnnotation(PanamaCIRCTConverter.convert(circuit, annotations.collectFirst { + case FirtoolOptionsAnnotation(firtoolOptions) => firtoolOptions + }))) case a => Seq(a) } } diff --git a/panamaconverter/src/PanamaCIRCTConverter.scala b/panamaconverter/src/PanamaCIRCTConverter.scala index f11fca9514b..8b3b84ebac9 100644 --- a/panamaconverter/src/PanamaCIRCTConverter.scala +++ b/panamaconverter/src/PanamaCIRCTConverter.scala @@ -17,6 +17,7 @@ import chisel3.internal.firrtl.Converter import chisel3.assert.{Assert => VerifAssert} import chisel3.assume.{Assume => VerifAssume} import chisel3.cover.{Cover => VerifCover} +import chisel3.panamalib.option.FirtoolOptions import chisel3.panamaom.PanamaCIRCTOM import chisel3.printf.{Printf => VerifPrintf} import chisel3.stop.{Stop => VerifStop} @@ -120,8 +121,7 @@ class FirContext { def rootWhen: Option[WhenContext] = Option.when(whenStack.nonEmpty)(whenStack.last) } -class PanamaCIRCTConverter { - val circt = new PanamaCIRCT +class PanamaCIRCTConverter(val circt: PanamaCIRCT, fos: Option[FirtoolOptions]) { val firCtx = new FirContext val mlirRootModule = circt.mlirModuleCreateEmpty(circt.unkLoc) @@ -880,7 +880,7 @@ class PanamaCIRCTConverter { assertResult(circt.mlirPassManagerRunOnOp(pm, circt.mlirModuleGetOperation(mlirRootModule))) } - def passManager(): PanamaCIRCTPassManager = new PanamaCIRCTPassManager(circt, mlirRootModule) + def passManager(): PanamaCIRCTPassManager = new PanamaCIRCTPassManager(circt, mlirRootModule, fos) def om(): PanamaCIRCTOM = new PanamaCIRCTOM(circt, mlirRootModule) def visitCircuit(name: String): Unit = { @@ -1617,8 +1617,11 @@ class PanamaCIRCTConverter { } private[panamaconverter] object PanamaCIRCTConverter { - def convert(circuit: Circuit): PanamaCIRCTConverter = { - implicit val cvt = new PanamaCIRCTConverter + def convert(circuit: Circuit, firtoolOptions: Option[FirtoolOptions]): PanamaCIRCTConverter = { + // TODO: In the future, we need to split PanamaCIRCT creation into a different public API. + // It provides a possibility for parsing mlirbc(OM requries it). + val circt = new PanamaCIRCT + implicit val cvt = new PanamaCIRCTConverter(circt, firtoolOptions) visitCircuit(circuit) cvt } diff --git a/panamaconverter/src/PanamaCIRCTPassManager.scala b/panamaconverter/src/PanamaCIRCTPassManager.scala index 8d5a490fd41..5a3f1494f24 100644 --- a/panamaconverter/src/PanamaCIRCTPassManager.scala +++ b/panamaconverter/src/PanamaCIRCTPassManager.scala @@ -3,10 +3,12 @@ package chisel3.panamaconverter import chisel3.panamalib._ +import chisel3.panamalib.option.FirtoolOptions +import chisel3.panamalib.option.PanamaFirtoolOption.FirtoolOptionsToPanama -private[panamaconverter] class PanamaCIRCTPassManager (circt: PanamaCIRCT, mlirModule: MlirModule) { +private[panamaconverter] class PanamaCIRCTPassManager (circt: PanamaCIRCT, mlirModule: MlirModule, fos: Option[FirtoolOptions]) { val pm = circt.mlirPassManagerCreate() - val options = circt.circtFirtoolOptionsCreateDefault() // TODO: Make it configurable from CIRCTPassManager + val options = fos.map(_.toPanama(circt)).getOrElse(circt.circtFirtoolOptionsCreateDefault()) private def isSuccess(result: MlirLogicalResult): Boolean = circt.mlirLogicalResultIsSuccess(result) diff --git a/panamalib/src/FirtoolOptions.scala b/panamalib/src/FirtoolOptions.scala new file mode 100644 index 00000000000..0cb8c32bb84 --- /dev/null +++ b/panamalib/src/FirtoolOptions.scala @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: Apache-2.0 + +// This should be the Scala API for user to invoke Firtool +// I(jiuyang) may want to promote it into a global user API for type safety in the userspace.(e.g. circt.options) +// It only declares types, converting them to cli/panama need to import corresponding implicit class +package chisel3.panamalib.option + +sealed trait FirtoolOption + +// All Firtool Options +case class AddMuxPragmas(value: Boolean) extends FirtoolOption +case class AddVivadoRAMAddressConflictSynthesisBugWorkaround(value: Boolean) extends FirtoolOption +case class BlackBoxRootPath(value: String) extends FirtoolOption +case class BuildMode(value: BuildModeEnum) extends FirtoolOption +case class ChiselInterfaceOutDirectory(value: String) extends FirtoolOption +case class CkgEnableName(value: String) extends FirtoolOption +case class CkgInputName(value: String) extends FirtoolOption +case class CkgModuleName(value: String) extends FirtoolOption +case class CkgOutputName(value: String) extends FirtoolOption +case class CkgTestEnableName(value: String) extends FirtoolOption +case class CompanionMode(value: CompanionModeEnum) extends FirtoolOption +case class DisableAggressiveMergeConnections(value: Boolean) extends FirtoolOption +case class DisableAnnotationsClassless(value: Boolean) extends FirtoolOption +case class DisableOptimization(value: Boolean) extends FirtoolOption +case class DisableRandom(value: RandomKindEnum) extends FirtoolOption +case class DisableUnknownAnnotations(value: Boolean) extends FirtoolOption +case class EmitChiselAssertsAsSVA(value: Boolean) extends FirtoolOption +case class EmitOmir(value: Boolean) extends FirtoolOption +case class EmitSeparateAlwaysBlocks(value: Boolean) extends FirtoolOption +case class EnableAnnotationWarning(value: Boolean) extends FirtoolOption +case class EtcDisableInstanceExtraction(value: Boolean) extends FirtoolOption +case class EtcDisableModuleInlining(value: Boolean) extends FirtoolOption +case class EtcDisableRegisterExtraction(value: Boolean) extends FirtoolOption +case class ExportChiselInterface(value: Boolean) extends FirtoolOption +case class ExportModuleHierarchy(value: Boolean) extends FirtoolOption +case class ExtractTestCode(value: Boolean) extends FirtoolOption +case class IgnoreReadEnableMem(value: Boolean) extends FirtoolOption +case class LowerAnnotationsNoRefTypePorts(value: Boolean) extends FirtoolOption +case class LowerMemories(value: Boolean) extends FirtoolOption +case class NoDedup(value: Boolean) extends FirtoolOption +case class OmirOutFile(value: String) extends FirtoolOption +case class OutputAnnotationFilename(value: String) extends FirtoolOption +case class OutputFilename(value: String) extends FirtoolOption +case class PreserveAggregate(value: PreserveAggregateModeEnum) extends FirtoolOption +case class PreserveValues(value: PreserveValuesModeEnum) extends FirtoolOption +case class ReplSeqMem(value: Boolean) extends FirtoolOption +case class ReplSeqMemFile(value: String) extends FirtoolOption +case class StripDebugInfo(value: Boolean) extends FirtoolOption +case class StripFirDebugInfo(value: Boolean) extends FirtoolOption +case class VbToBv(value: Boolean) extends FirtoolOption + +// All Enums +sealed trait BuildModeEnum +case object BuildModeDefault extends BuildModeEnum +case object BuildModeDebug extends BuildModeEnum +case object BuildModeRelease extends BuildModeEnum + +sealed trait CompanionModeEnum +case object CompanionModeBind extends CompanionModeEnum +case object CompanionModeInstantiate extends CompanionModeEnum +case object CompanionModeDrop extends CompanionModeEnum + +sealed trait RandomKindEnum +case object RandomKindNone extends RandomKindEnum +case object RandomKindMem extends RandomKindEnum +case object RandomKindReg extends RandomKindEnum +case object RandomKindAll extends RandomKindEnum + +sealed trait PreserveAggregateModeEnum +case object PreserveAggregateModeNone extends PreserveAggregateModeEnum +case object PreserveAggregateModeOneDimVec extends PreserveAggregateModeEnum +case object PreserveAggregateModeVec extends PreserveAggregateModeEnum +case object PreserveAggregateModeAll extends PreserveAggregateModeEnum + +sealed trait PreserveValuesModeEnum +case object PreserveValuesModeStrip extends PreserveValuesModeEnum +case object PreserveValuesModeNone extends PreserveValuesModeEnum +case object PreserveValuesModeNamed extends PreserveValuesModeEnum +case object PreserveValuesModeAll extends PreserveValuesModeEnum + +case class FirtoolOptions(options: Set[FirtoolOption]) diff --git a/panamalib/src/PanamaFirtoolOption.scala b/panamalib/src/PanamaFirtoolOption.scala new file mode 100644 index 00000000000..d9574e653e7 --- /dev/null +++ b/panamalib/src/PanamaFirtoolOption.scala @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: Apache-2.0 + +package chisel3.panamalib.option + +import chisel3.panamalib._ + +object PanamaFirtoolOption { + implicit class FirtoolOptionToPanama(fo: FirtoolOption) { + def toPanama(panamaCIRCT: PanamaCIRCT, options: CirctFirtoolFirtoolOptions): Unit = fo match { + // format: off + case AddMuxPragmas(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetAddMuxPragmas(options, value) + case AddVivadoRAMAddressConflictSynthesisBugWorkaround(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetAddVivadoRAMAddressConflictSynthesisBugWorkaround(options, value) + case BlackBoxRootPath(value: String) => panamaCIRCT.circtFirtoolOptionsSetBlackBoxRootPath(options, value) + case BuildMode(value: BuildModeEnum) => panamaCIRCT.circtFirtoolOptionsSetBuildMode(options, value) + case ChiselInterfaceOutDirectory(value: String) => panamaCIRCT.circtFirtoolOptionsSetChiselInterfaceOutDirectory(options, value) + case CkgEnableName(value: String) => panamaCIRCT.circtFirtoolOptionsSetCkgEnableName(options, value) + case CkgInputName(value: String) => panamaCIRCT.circtFirtoolOptionsSetCkgInputName(options, value) + case CkgModuleName(value: String) => panamaCIRCT.circtFirtoolOptionsSetCkgModuleName(options, value) + case CkgOutputName(value: String) => panamaCIRCT.circtFirtoolOptionsSetCkgOutputName(options, value) + case CkgTestEnableName(value: String) => panamaCIRCT.circtFirtoolOptionsSetCkgTestEnableName(options, value) + case CompanionMode(value: CompanionModeEnum) => panamaCIRCT.circtFirtoolOptionsSetCompanionMode(options, value) + case DisableAggressiveMergeConnections(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetDisableAggressiveMergeConnections(options, value) + case DisableAnnotationsClassless(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetDisableAnnotationsClassless(options, value) + case DisableOptimization(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetDisableOptimization(options, value) + case DisableRandom(value: RandomKindEnum) => panamaCIRCT.circtFirtoolOptionsSetDisableRandom(options, value) + case DisableUnknownAnnotations(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetDisableUnknownAnnotations(options, value) + case EmitChiselAssertsAsSVA(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetEmitChiselAssertsAsSVA(options, value) + case EmitOmir(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetEmitOmir(options, value) + case EmitSeparateAlwaysBlocks(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetEmitSeparateAlwaysBlocks(options, value) + case EnableAnnotationWarning(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetEnableAnnotationWarning(options, value) + case EtcDisableInstanceExtraction(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetEtcDisableInstanceExtraction(options, value) + case EtcDisableModuleInlining(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetEtcDisableModuleInlining(options, value) + case EtcDisableRegisterExtraction(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetEtcDisableRegisterExtraction(options, value) + case ExportChiselInterface(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetExportChiselInterface(options, value) + case ExportModuleHierarchy(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetExportModuleHierarchy(options, value) + case ExtractTestCode(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetExtractTestCode(options, value) + case IgnoreReadEnableMem(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetIgnoreReadEnableMem(options, value) + case LowerAnnotationsNoRefTypePorts(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetLowerAnnotationsNoRefTypePorts(options, value) + case LowerMemories(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetLowerMemories(options, value) + case NoDedup(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetNoDedup(options, value) + case OmirOutFile(value: String) => panamaCIRCT.circtFirtoolOptionsSetOmirOutFile(options, value) + case OutputAnnotationFilename(value: String) => panamaCIRCT.circtFirtoolOptionsSetOutputAnnotationFilename(options, value) + case OutputFilename(value: String) => panamaCIRCT.circtFirtoolOptionsSetOutputFilename(options, value) + case PreserveAggregate(value: PreserveAggregateModeEnum) => panamaCIRCT.circtFirtoolOptionsSetPreserveAggregate(options, value) + case PreserveValues(value: PreserveValuesModeEnum) => panamaCIRCT.circtFirtoolOptionsSetPreserveValues(options, value) + case ReplSeqMem(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetReplSeqMem(options, value) + case ReplSeqMemFile(value: String) => panamaCIRCT.circtFirtoolOptionsSetReplSeqMemFile(options, value) + case StripDebugInfo(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetStripDebugInfo(options, value) + case StripFirDebugInfo(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetStripFirDebugInfo(options, value) + case VbToBv(value: Boolean) => panamaCIRCT.circtFirtoolOptionsSetVbToBv(options, value) + // format: on + } + } + implicit class FirtoolOptionsToPanama(fos: FirtoolOptions) { + def toPanama(panamaCIRCT: PanamaCIRCT): CirctFirtoolFirtoolOptions = { + val firtoolOptions = panamaCIRCT.circtFirtoolOptionsCreateDefault() + fos.options.foreach(fo => fo.toPanama(panamaCIRCT, firtoolOptions)) + firtoolOptions + } + } + + implicit def buildModeEnumtoPanama(e: BuildModeEnum): CirctFirtoolBuildMode = e match { + case BuildModeDefault => CirctFirtoolBuildMode.Default + case BuildModeDebug => CirctFirtoolBuildMode.Debug + case BuildModeRelease => CirctFirtoolBuildMode.Release + } + implicit def companionModeEnumtoPanama(e: CompanionModeEnum): CirctFirtoolCompanionMode = e match { + case CompanionModeBind => CirctFirtoolCompanionMode.Bind + case CompanionModeInstantiate => CirctFirtoolCompanionMode.Instantiate + case CompanionModeDrop => CirctFirtoolCompanionMode.Drop + } + implicit def randomKindEnumtoPanama(e: RandomKindEnum): CirctFirtoolRandomKind = e match { + case RandomKindNone => CirctFirtoolRandomKind.None + case RandomKindMem => CirctFirtoolRandomKind.Mem + case RandomKindReg => CirctFirtoolRandomKind.Reg + case RandomKindAll => CirctFirtoolRandomKind.All + } + implicit def preserveAggregateModeEnumtoPanama(e: PreserveAggregateModeEnum): CirctFirtoolPreserveAggregateMode = + e match { + case PreserveAggregateModeNone => CirctFirtoolPreserveAggregateMode.None + case PreserveAggregateModeOneDimVec => CirctFirtoolPreserveAggregateMode.OneDimVec + case PreserveAggregateModeVec => CirctFirtoolPreserveAggregateMode.Vec + case PreserveAggregateModeAll => CirctFirtoolPreserveAggregateMode.All + } + implicit def preserveValuesModeEnumtoPanama(e: PreserveValuesModeEnum): CirctFirtoolPreserveValuesMode = e match { + case PreserveValuesModeStrip => CirctFirtoolPreserveValuesMode.Strip + case PreserveValuesModeNone => CirctFirtoolPreserveValuesMode.None + case PreserveValuesModeNamed => CirctFirtoolPreserveValuesMode.Named + case PreserveValuesModeAll => CirctFirtoolPreserveValuesMode.All + } +} From 4520d304ec152fba10fe89088b09d4d819cdb3bd Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Mon, 29 Jan 2024 03:18:19 +0800 Subject: [PATCH 2/4] add test api for FirtoolOptions --- lit/utility/src/package.scala | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/lit/utility/src/package.scala b/lit/utility/src/package.scala index 3391e4865a4..0047af1c16f 100644 --- a/lit/utility/src/package.scala +++ b/lit/utility/src/package.scala @@ -1,10 +1,12 @@ import chisel3._ import chisel3.panamaconverter.PanamaCIRCTConverter +import chisel3.panamalib.option.FirtoolOptions +import chisel3.panamaom.PanamaCIRCTOMEvaluator package object lit { object utility { object panamaconverter { - def getConverter(module: => RawModule): PanamaCIRCTConverter = Seq( + def getConverter(module: => RawModule, firtoolOptions: FirtoolOptions = FirtoolOptions(Set.empty)): PanamaCIRCTConverter = Seq( new chisel3.stage.phases.Elaborate, chisel3.panamaconverter.stage.Convert ).foldLeft( @@ -14,16 +16,25 @@ package object lit { converter }.get - def streamString(module: => RawModule, stream: PanamaCIRCTConverter => geny.Writable): String = { + def runAllPass(converter: PanamaCIRCTConverter) = { + val pm = converter.passManager() + assert(pm.populatePreprocessTransforms()) + assert(pm.populateCHIRRTLToLowFIRRTL()) + assert(pm.populateLowFIRRTLToHW()) + assert(pm.populateFinalizeIR()) + assert(pm.run()) + } + + def streamString(module: => RawModule, firtoolOptions: FirtoolOptions = FirtoolOptions(Set.empty), stream: PanamaCIRCTConverter => geny.Writable): String = { val converter = getConverter(module) val string = new java.io.ByteArrayOutputStream stream(converter).writeBytesTo(string) new String(string.toByteArray) } - def firrtlString(module: => RawModule): String = streamString(module, _.firrtlStream) + def firrtlString(module: => RawModule, firtoolOptions: FirtoolOptions = FirtoolOptions(Set.empty)): String = streamString(module, firtoolOptions, _.firrtlStream) - def verilogString(module: => RawModule): String = streamString(module, _.verilogStream) + def verilogString(module: => RawModule, firtoolOptions: FirtoolOptions = FirtoolOptions(Set.empty)): String = streamString(module, firtoolOptions, _.verilogStream) } } } From 72f6c9d6d5af56df3250f1c3ecb8d2b705f0b6b8 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Mon, 29 Jan 2024 03:21:04 +0800 Subject: [PATCH 3/4] draft tests for FirtoolOptions --- lit/tests/FirtoolOptions.sc | 45 +++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 lit/tests/FirtoolOptions.sc diff --git a/lit/tests/FirtoolOptions.sc b/lit/tests/FirtoolOptions.sc new file mode 100644 index 00000000000..5ecbdab1616 --- /dev/null +++ b/lit/tests/FirtoolOptions.sc @@ -0,0 +1,45 @@ +// RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" --java-opt="--enable-native-access=ALL-UNNAMED" --java-opt="--enable-preview" --java-opt="-Djava.library.path=%JAVALIBRARYPATH" %s -- panama-verilog | FileCheck %s -check-prefix=VERILOG + +import chisel3._ +import chisel3.panamalib.option._ + +// println(lit.utility.panamaconverter.verilogString(???, Set(AddMuxPragmas(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(AddVivadoRAMAddressConflictSynthesisBugWorkaround(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(BlackBoxRootPath(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(BuildMode(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(ChiselInterfaceOutDirectory(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(CkgEnableName(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(CkgInputName(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(CkgModuleName(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(CkgOutputName(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(CkgTestEnableName(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(CompanionMode(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(DisableAggressiveMergeConnections(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(DisableAnnotationsClassless(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(DisableOptimization(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(DisableRandom(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(DisableUnknownAnnotations(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(EmitChiselAssertsAsSVA(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(EmitOmir(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(EmitSeparateAlwaysBlocks(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(EnableAnnotationWarning(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(EtcDisableInstanceExtraction(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(EtcDisableModuleInlining(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(EtcDisableRegisterExtraction(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(ExportChiselInterface(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(ExportModuleHierarchy(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(ExtractTestCode(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(IgnoreReadEnableMem(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(LowerAnnotationsNoRefTypePorts(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(LowerMemories(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(NoDedup(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(OmirOutFile(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(OutputAnnotationFilename(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(OutputFilename(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(PreserveAggregate(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(PreserveValues(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(ReplSeqMem(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(ReplSeqMemFile(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(StripDebugInfo(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(StripFirDebugInfo(???)))) +// println(lit.utility.panamaconverter.verilogString(???, Set(VbToBv(???)))) \ No newline at end of file From 3537227e22e0c990afbb41eeacca23cc3803f4f6 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Mon, 29 Jan 2024 03:43:27 +0800 Subject: [PATCH 4/4] add false check for Property --- lit/tests/Property/Bad.sc | 11 +++++++ lit/tests/{OMTest.sc => Property/Good.sc} | 39 ++++++++++++++++------- 2 files changed, 39 insertions(+), 11 deletions(-) create mode 100644 lit/tests/Property/Bad.sc rename lit/tests/{OMTest.sc => Property/Good.sc} (54%) diff --git a/lit/tests/Property/Bad.sc b/lit/tests/Property/Bad.sc new file mode 100644 index 00000000000..5e18ca8bf24 --- /dev/null +++ b/lit/tests/Property/Bad.sc @@ -0,0 +1,11 @@ +// RUN: not scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" %s -- 2>&1 | FileCheck %s + +import chisel3.properties._ + +class MyLit +// CHECK: error: unsupported Property type Bad.MyLit +val badPropLiteral = Property(new MyLit) + +// CHECK: error: unsupported Property type Bad.MyTpe +class MyTpe +val badPropType = Property[MyTpe]() diff --git a/lit/tests/OMTest.sc b/lit/tests/Property/Good.sc similarity index 54% rename from lit/tests/OMTest.sc rename to lit/tests/Property/Good.sc index 8f90664f109..f26ee8ac372 100644 --- a/lit/tests/OMTest.sc +++ b/lit/tests/Property/Good.sc @@ -1,9 +1,30 @@ -// RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" --java-opt="--enable-native-access=ALL-UNNAMED" --java-opt="--enable-preview" --java-opt="-Djava.library.path=%JAVALIBRARYPATH" %s -- panama-omstring | FileCheck %s +// RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" %s -- chirrtl | FileCheck %s -check-prefix=SFC-FIRRTL +// RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" --java-opt="--enable-native-access=ALL-UNNAMED" --java-opt="--enable-preview" --java-opt="-Djava.library.path=%JAVALIBRARYPATH" %s -- panama-om | FileCheck %s -check-prefix=MFC-OM import chisel3._ import chisel3.properties._ import chisel3.panamaom._ -import chisel3.panamaconverter._ +import lit.utility._ + +// SFC-FIRRTL-LABEL: circuit IntPropTest : +// SFC-FIRRTL-NEXT: module IntPropTest : +// SFC-FIRRTL-NEXT: output intProp : Integer + +// MFC-OM-LABEL: circuit IntPropTest : +// MFC-OM-NEXT: module IntPropTest : +// MFC-OM-NEXT: output intProp : Integer +class IntPropTest extends RawModule { + val intProp = IO(Output(Property[Int]())) + intProp := Property(1) +} + +args.head match { + case "chirrtl" => + println(circt.stage.ChiselStage.emitCHIRRTL(new IntPropTest)) + case "panama-om" => + println(lit.utility.panamaconverter.firrtlString(new IntPropTest)) + case _ => +} class PropertyTest extends RawModule { val i = IO(Input(UInt(8.W))) @@ -18,14 +39,9 @@ class PropertyTest extends RawModule { } args.head match { - case "panama-omstring" => - val converter: PanamaCIRCTConverter = lit.utility.panamaconverter.getConverter(new PropertyTest) - val pm = converter.passManager() - assert(pm.populatePreprocessTransforms()) - assert(pm.populateCHIRRTLToLowFIRRTL()) - assert(pm.populateLowFIRRTLToHW()) - assert(pm.populateFinalizeIR()) - assert(pm.run()) + case "panama-om" => + val converter = lit.utility.panamaconverter.getConverter(new PropertyTest) + lit.utility.panamaconverter.runAllPass(converter) val om = converter.om() val evaluator = om.evaluator() @@ -38,4 +54,5 @@ args.head match { // CHECK-NEXT: .b => { [ [ prim{omInteger{456}} ] ] } // CHECK-NEXT: .p => { path{OMReferenceTarget:~PropertyTest|PropertyTest>i} } obj.foreachField((name, value) => println(s".$name => { ${value.display} }")) -} + case _ => +} \ No newline at end of file