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Fix 0 width signals chiselsim #4100

Merged
merged 4 commits into from
May 28, 2024
Merged

Fix 0 width signals chiselsim #4100

merged 4 commits into from
May 28, 2024

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rameloni
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Fixes #4099

Contributor Checklist

  • Did you add Scaladoc to every public function/method?
  • Did you add at least one test demonstrating the PR?
  • Did you delete any extraneous printlns/debugging code?
  • Did you specify the type of improvement?
  • Did you add appropriate documentation in docs/src?
  • Did you request a desired merge strategy?
  • Did you add text to be included in the Release Notes for this change?

Type of Improvement

  • Bugfix

Desired Merge Strategy

  • Squash: The PR will be squashed and merged (choose this if you have no preference).

Release Notes

Fix failing ChiselSim/SVsim error to simulate modules with zero-width ports.

Reviewer Checklist (only modified by reviewer)

  • Did you add the appropriate labels? (Select the most appropriate one based on the "Type of Improvement")
  • Did you mark the proper milestone (Bug fix: 3.6.x, 5.x, or 6.x depending on impact, API modification or big change: 7.0)?
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sequencer
sequencer approved these changes May 25, 2024
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LGTM

@jackkoenig jackkoenig added the Bugfix Fixes a bug, will be included in release notes label May 28, 2024
jackkoenig
jackkoenig approved these changes May 28, 2024
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Some minor nits but LGTM!

@jackkoenig jackkoenig added this to the 5.x milestone May 28, 2024
@jackkoenig jackkoenig enabled auto-merge (squash) May 28, 2024 21:53
@jackkoenig jackkoenig merged commit 2f9faa2 into chipsalliance:main May 28, 2024
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@mergify mergify bot added the Backported This PR has been backported label May 28, 2024
mergify bot pushed a commit that referenced this pull request May 28, 2024
@rameloni @mergify
Fix 0 width signals chiselsim (#4100)
ff18e94 
(cherry picked from commit 2f9faa2)

# Conflicts:
#	src/test/scala/chiselTests/simulator/SimulatorSpec.scala
mergify bot pushed a commit that referenced this pull request May 28, 2024
@rameloni @mergify
Fix 0 width signals chiselsim (#4100)
3929503 
(cherry picked from commit 2f9faa2)

# Conflicts:
#	src/test/scala/chiselTests/simulator/SimulatorSpec.scala
This was referenced May 28, 2024
Merged
Merged
chiselbot pushed a commit that referenced this pull request May 29, 2024
@mergify @rameloni @jackkoenig
Fix 0 width signals chiselsim (backport #4100) (#4103)
de4d945 
* Fix 0 width signals chiselsim (#4100)

(cherry picked from commit 2f9faa2)

# Conflicts:
#	src/test/scala/chiselTests/simulator/SimulatorSpec.scala

* Resolve backport conflicts

---------

Co-authored-by: Raffaele Meloni <raffaele.meloni99@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
chiselbot pushed a commit that referenced this pull request May 29, 2024
@mergify @rameloni @jackkoenig
Fix 0 width signals chiselsim (backport #4100) (#4104)
680f043 
* Fix 0 width signals chiselsim (#4100)

(cherry picked from commit 2f9faa2)

# Conflicts:
#	src/test/scala/chiselTests/simulator/SimulatorSpec.scala

* Resolve backport conflicts

---------

Co-authored-by: Raffaele Meloni <raffaele.meloni99@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
@rameloni rameloni deleted the fix-0-width-signals-chiselsim branch May 30, 2024 08:31
@rameloni rameloni restored the fix-0-width-signals-chiselsim branch May 30, 2024 08:33
@rameloni rameloni deleted the fix-0-width-signals-chiselsim branch June 27, 2024 15:15
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@sequencer sequencer sequencer approved these changes

@jackkoenig jackkoenig jackkoenig approved these changes

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Successfully merging this pull request may close these issues.

ChiselSim fails to simulate circuit with optional (0-width) ports
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@rameloni @sequencer @jackkoenig