Add map method for Valid

[tymcauley]

Modeled after #2646.

Contributor Checklist

• Did you add Scaladoc to every public function/method?
• Did you add at least one test demonstrating the PR?
• Did you delete any extraneous printlns/debugging code?
• Did you specify the type of improvement?
• Did you add appropriate documentation in docs/src?
• Did you request a desired merge strategy?
• Did you add text to be included in the Release Notes for this change?

Type of Improvement

• Feature (or new API)

Desired Merge Strategy

Squash

Release Notes

Users can now apply a function f to the bits field of a Valid instance with the new Valid.map(f) method.

Reviewer Checklist (only modified by reviewer)

• Did you add the appropriate labels? (Select the most appropriate one based on the "Type of Improvement")
• Did you mark the proper milestone (Bug fix: 3.6.x, 5.x, or 6.x depending on impact, API modification or big change: 7.0)?
• Did you review?
• Did you check whether all relevant Contributor checkboxes have been checked?
• Did you do one of the following when ready to merge:
  • Squash: You/ the contributor Enable auto-merge (squash), clean up the commit message, and label with Please Merge.
  • Merge: Ensure that contributor has cleaned up their commit history, then merge with Create a merge commit.

[tymcauley]

For those curious, here's the result of emitSystemVerilog for each of the three tests:

// Generated by CIRCT firtool-1.76.0-1-g086a19f12
module ValidSpec_Anon(
  input        clock,
               reset,
               in_valid,
  input  [7:0] in_bits,
  output       out_valid,
  output [7:0] out_bits
);

  assign out_valid = in_valid;
  assign out_bits = in_bits + 8'h1;
endmodule

// Generated by CIRCT firtool-1.76.0-1-g086a19f12
module ValidSpec_Anon(
  input        clock,
               reset,
               in_valid,
  input  [7:0] in_bits_foo,
               in_bits_bar,
  input        in_bits_fizz,
               in_bits_buzz,
  output       out_valid,
  output [7:0] out_bits_foo,
               out_bits_bar,
  output       out_bits_fizz,
               out_bits_buzz
);

  assign out_valid = in_valid;
  assign out_bits_foo = in_bits_foo + 8'h1;
  assign out_bits_bar = in_bits_bar - 8'h1;
  assign out_bits_fizz = 1'h0;
  assign out_bits_buzz = 1'h1;
endmodule

// Generated by CIRCT firtool-1.76.0-1-g086a19f12
module ValidSpec_Anon(
  input        clock,
               reset,
               in_valid,
  input  [7:0] in_bits_foo,
               in_bits_bar,
  output       out_valid,
  output [7:0] out_bits
);

  assign out_valid = in_valid;
  assign out_bits = in_bits_foo & in_bits_bar;
endmodule

[jackkoenig]

Nice!