diff --git a/src/main/scala/firrtl/passes/ZeroWidth.scala b/src/main/scala/firrtl/passes/ZeroWidth.scala
index 5bf4d33921..b14f012d0a 100644
--- a/src/main/scala/firrtl/passes/ZeroWidth.scala
+++ b/src/main/scala/firrtl/passes/ZeroWidth.scala
@@ -11,27 +11,6 @@ object ZeroWidth extends Transform {
   def inputForm: CircuitForm = UnknownForm
   def outputForm: CircuitForm = UnknownForm
 
-<<<<<<< HEAD
-  private def makeEmptyMemBundle(name: String): Field =
-    Field(name, Flip, BundleType(Seq(
-      Field("addr", Default, UIntType(IntWidth(0))),
-      Field("en",   Default, UIntType(IntWidth(0))),
-      Field("clk",  Default, UIntType(IntWidth(0))),
-      Field("data", Flip,    UIntType(IntWidth(0)))
-    )))
-
-  private def onEmptyMemStmt(s: Statement): Statement = s match {
-    case d @ DefMemory(info, name, tpe, _, _, _, rs, ws, rws, _) => removeZero(tpe) match {
-      case None =>
-        DefWire(info, name, BundleType(
-          rs.map(r => makeEmptyMemBundle(r)) ++
-          ws.map(w => makeEmptyMemBundle(w)) ++
-          rws.map(rw => makeEmptyMemBundle(rw))
-        ))
-      case Some(_) => d
-    }
-    case sx => sx map onEmptyMemStmt
-=======
   private def makeZero(tpe: ir.Type): ir.Type = tpe match {
     case ClockType => UIntType(IntWidth(0))
     case a: UIntType      => a.copy(IntWidth(0))
@@ -53,7 +32,6 @@ object ZeroWidth extends Transform {
         case Some(_) => d
       }
     case sx => sx.map(onEmptyMemStmt)
->>>>>>> 67ce97a1... Fix bug in zero-width memory removal (#2153)
   }
 
   private def onModuleEmptyMemStmt(m: DefModule): DefModule = {