From 2768b865527591becfb702686d316997ccd60fcb Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Sat, 13 Mar 2021 22:33:50 -0800 Subject: [PATCH] Fix width of constant propagation of SInt with zero --- .../firrtl/transforms/ConstantPropagation.scala | 2 +- .../firrtlTests/ConstantPropagationTests.scala | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/main/scala/firrtl/transforms/ConstantPropagation.scala b/src/main/scala/firrtl/transforms/ConstantPropagation.scala index 0523082dd2..7106c699e7 100644 --- a/src/main/scala/firrtl/transforms/ConstantPropagation.scala +++ b/src/main/scala/firrtl/transforms/ConstantPropagation.scala @@ -230,7 +230,7 @@ class ConstantPropagation extends Transform with DependencyAPIMigration { } def simplify(e: Expression, lhs: Literal, rhs: Expression) = lhs match { case UIntLiteral(v, _) if v == BigInt(0) => rhs - case SIntLiteral(v, _) if v == BigInt(0) => asUInt(rhs, e.tpe) + case SIntLiteral(v, _) if v == BigInt(0) => asUInt(pad(rhs, e.tpe), e.tpe) case UIntLiteral(v, IntWidth(w)) if v == (BigInt(1) << bitWidth(rhs.tpe).toInt) - 1 => lhs case _ => e } diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala index 28c1d823cf..60cf1b8be8 100644 --- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala +++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala @@ -1638,6 +1638,20 @@ class ConstantPropagationEquivalenceSpec extends FirrtlFlatSpec { firrtlEquivalenceTest(input, transforms) } + // https://github.com/chipsalliance/firrtl/issues/2034 + "SInt OR with constant zero" should "have the correct widths" in { + val input = + s"""circuit WidthsOrSInt : + | module WidthsOrSInt : + | input in : SInt<1> + | input in2 : SInt<4> + | output out : UInt<8> + | output out2 : UInt<8> + | out <= or(in, SInt<8>(0)) + | out2 <= or(in2, SInt<8>(0))""".stripMargin + firrtlEquivalenceTest(input, transforms) + } + "addition by zero width wires" should "have the correct widths" in { val input = s"""circuit ZeroWidthAdd: