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Bump to Chisel v3.3.0 and FIRRTL v1.3.0 #2399

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merged 1 commit into from
May 5, 2020
Merged

Bump to Chisel v3.3.0 and FIRRTL v1.3.0 #2399

merged 1 commit into from
May 5, 2020

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jackkoenig
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@jackkoenig jackkoenig commented Apr 6, 2020

  • Update some uses of @chiselName to disable new prefixing behavior
  • Update Stage/Phase dependencies to new Dependency instead of Class
  • Technically bumped to merge-base of each tag with their respective
    release branches: 3.3.x for chisel3 and 1.3.x for firrtl
    This better supports Wit dependencies
  • Include all chisel3 class files on FIRRTL run classpath

We include chisel3 on the classpath for running FIRRTL because of use of utils like chisel3.util.HasBlackBoxResource. chipsalliance/chisel#1384 broke up the chisel3 build into multiple directories so I had to update the Makefiles to include the extra directories.

TODO Release Notes Highlights

Related issue:

Type of change: other enhancement

Impact: API modification

Development Phase: implementation

Release Notes
Bump to Chisel v3.3.0-RC3 and FIRRTL v1.3.0-RC3. Chisel and FIRRTL use a versioning scheme X.Y.Z where Y signifies major version and thus may contain backwards incompatible API changes. See their respective release notes (currently in draft):
https://github.com/freechipsproject/chisel3/releases
https://github.com/freechipsproject/firrtl/releases

@jackkoenig jackkoenig changed the title Bump to Chisel v3.3.0-RC1 and FIRRTL v1.3.0-RC1 Bump to Chisel v3.3.0-RC3 and FIRRTL v1.3.0-RC3 Apr 23, 2020
@jackkoenig
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This has been updated to RC3, it currently will fail the Wake compilation test because I need to update api-chisel3-sifive and api-firrtl-sifive, but the functionality should be correct.

@jackkoenig jackkoenig force-pushed the chisel-3-3 branch 2 times, most recently from 9e5ba63 to de7456b Compare April 25, 2020 01:13
@mwachs5
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mwachs5 commented Apr 27, 2020

the two failign tests looked like transient maven issues so i kicked them off again

@jackkoenig jackkoenig force-pushed the chisel-3-3 branch 2 times, most recently from 60522fa to 9f5e3c4 Compare May 1, 2020 21:08
@jackkoenig jackkoenig changed the title Bump to Chisel v3.3.0-RC3 and FIRRTL v1.3.0-RC3 Bump to Chisel v3.3.0 and FIRRTL v1.3.0 May 1, 2020
@mwachs5
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mwachs5 commented May 2, 2020

Does this include the workaround chipsalliance/firrtl#1556?

@jackkoenig
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Does this include the workaround chipsalliance/firrtl#1556?

Not yet, I was thinking about copy-pasting the code here and then removing it on the next bump but I could also just try to get the fix in and backported and then we can bump along the stable branch, a bit past 1.3.0.

* Update some uses of @chiselName to disable new prefixing behavior
* Update Stage/Phase dependencies to new Dependency instead of Class
* Technically bumped to merge-base of each tag with their respective
  release branches: 3.3.x for chisel3 and 1.3.x for firrtl
  This better supports Wit dependencies
* Include all chisel3 class files on FIRRTL run classpath
* Bump api-chisel3-sifive to resolve Wit conflicts and bump
  api-scala-sifive to support Wit >= v0.13.0
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3 participants