flow_discrete_RTPG.ys

# VHDL to Discrete RT+Pass gate-logic


# elaborate VHDL code from GHDL
ghdl
hierarchy -check

flatten

# Rename top entity to 'main'. This is important, otherwise other parts of the flow may break.
rename -top main

# Read verilog description of cells
read_verilog -lib ../20_SYNTH/discrete_RTPG_logic_cells.v

# Draw netlist of elaborated design
show -format pdf -prefix 200_diagramm_hdl_elaborated

# Insert tristate buffers (ATTENTION: Currently not a supported cell type during P&R)
tribuf

# Technology mapping
techmap

proc; opt; 

techmap -map ../20_SYNTH/discrete_RTPG_techmap.v   # map TBUF

#proc; opt; fsm; opt; 
dfflibmap -liberty ../20_SYNTH/discrete_RTPG_logic_liberty.lib
proc; opt;
abc -liberty ../20_SYNTH/discrete_RTPG_logic_liberty.lib
opt_clean -purge

# Print Statistics
stat -liberty ../20_SYNTH/discrete_RTPG_logic_liberty.lib

# Draw netlist of optimized and mapped design
show -format pdf -prefix 208_diagramm_after_mapping


# Write out in spice format
write_spice 209_synthesized_output.sp
write_json  210_synthesized_output.json